SN74LV574AOctal Edge-Triggered D-Type Flip-Flops With 3-State Outputs | Flip Flops | 8 | Active | The ’LV574A devices are octal edge-triggered D-type flip-flops designed for 2 V to 5.5 V VCCoperation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
The ’LV574A devices are octal edge-triggered D-type flip-flops designed for 2 V to 5.5 V VCCoperation.
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. |
SN74LV594AEight-bit shift registers with output registers | Shift Registers | 13 | Active | The SN74LV594A devices are 8-bit shift registers designed for 2 V to 5.5 V VCCoperation.
The SN74LV594A devices are 8-bit shift registers designed for 2 V to 5.5 V VCCoperation. |
SN74LV595A-Q1Automotive 8-bit shift registers with 3-state output registers | Shift Registers | 14 | Active | The SN74LV595A-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.
The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LV595A-Q1 contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.
The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LV595B-EPEnhanced product eight-bit shift registers with tri-state output registers | Shift Registers | 1 | Active | The SN74LV595B-EP contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.
The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LV595B-EP contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state.
The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LV6T061.8-V to 5.5-V single power supply 6-bit inverters with tri-state outputs | Integrated Circuits (ICs) | 1 | Active | The SN74LV6T06 device contains six independent inverters with open-drain outputs. Each inverter performs the Boolean function Y = A in positive logic.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
The SN74LV6T06 device contains six independent inverters with open-drain outputs. Each inverter performs the Boolean function Y = A in positive logic.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output). |
SN74LV6T06-EPEnhanced-product, six-bit inverting open-drain fixed-direction level translator | Buffers, Drivers, Receivers, Transceivers | 1 | Active | The SN74LV6T06-EP device contains six independent inverters with open-drain outputs and extended voltage operation to allow for level translation. Each inverter performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).
The SN74LV6T06-EP device contains six independent inverters with open-drain outputs and extended voltage operation to allow for level translation. Each inverter performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output). |
SN74LV6T06-Q1Automotive 1.8-V to 5.5-V single power supply 6-bit inverters with tri-state outputs | Logic | 1 | Active | The SN74LV6T06-Q1 device contains six independent inverters with open-drain outputs. Each inverter performs the Boolean function Y = A in positive logic.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
The SN74LV6T06-Q1 device contains six independent inverters with open-drain outputs. Each inverter performs the Boolean function Y = A in positive logic.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output). |
SN74LV6T071.8-V to 5.5-V single power supply 6-bit buffers with tri-state outputs | Integrated Circuits (ICs) | 1 | Active | The SN74LV6T07 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
The SN74LV6T07 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output). |
SN74LV6T07-Q1Automotive 1.8-V to 5.5-V single power supply 6-bit buffers with tri-state outputs | Buffers, Drivers, Receivers, Transceivers | 2 | Active | The SN74LV6T07-Q1 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
The SN74LV6T07-Q1 device contains six independent buffers with open-drain outputs. Each buffer performs the Boolean function Y = A in positive logic.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output). |
SN74LV6T141.8-V to 5.5-V single power supply 6-bit inverters with tri-state outputs | Logic | 2 | Active | The SN74LV6T14 device contains six independent Inverter with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).
The SN74LV6T14 device contains six independent Inverter with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output). |
