SN74LV595B-EP Series

Enhanced product eight-bit shift registers with tri-state output registers

Catalog

Enhanced product eight-bit shift registers with tri-state output registers

Part	Operating Temperature [Min]	Operating Temperature [Max]	Function	Mounting Type	Number of Bits per Element	Supplier Device Package	Output Type	Package / Case [x]	Package / Case	Package / Case [y]	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Elements
Texas Instruments SN74LV595BMPWREP	-55 °C	125 °C	Serial to Parallel Serial	Surface Mount	8	16-TSSOP	Tri-State	0.173 in	16-TSSOP	4.4 mm	5.5 V	2 V	1

Catalog

Enhanced product eight-bit shift registers with tri-state output registers

Key Features

• 2 V to 5.5 V V CC operationSupports mixed-mode voltage operation on all portsI off supports partial-power-down mode operationLatch-up performance exceeds 250 mA per JESD 17Operating ambient temperature: -55°C to +125°CSupports defense, aerospace, and medical applications:Controlled baselineOne assembly and test siteOne fabrication siteExtended product life cycleProduct traceability2 V to 5.5 V V CC operationSupports mixed-mode voltage operation on all portsI off supports partial-power-down mode operationLatch-up performance exceeds 250 mA per JESD 17Operating ambient temperature: -55°C to +125°CSupports defense, aerospace, and medical applications:Controlled baselineOne assembly and test siteOne fabrication siteExtended product life cycleProduct traceability

Description

The SN74LV595B-EP contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state. The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74LV595B-EP contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear ( SRCLR) input, serial (SER) input, and a serial output for cascading. When the output-enable ( OE) input is high, all outputs except Q H’ are in the high-impedance state. The device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.