SN74LV6T06-EP Series

Enhanced-product, six-bit inverting open-drain fixed-direction level translator

Catalog

Enhanced-product, six-bit inverting open-drain fixed-direction level translator

Part	Number of Bits per Element	Voltage - Supply [Min]	Voltage - Supply [Max]	Current - Output High, Low	Current - Output High, Low	Package / Case [custom]	Package / Case [custom]	Package / Case	Logic Type	Output Type	Supplier Device Package	Number of Elements	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments SN74LV6T06PWREP	1	1.6 V	5.5 V	8 mA	-	0.173 "	4.4 mm	14-TSSOP	Buffer Non-Inverting	Open Drain	14-TSSOP	6	Surface Mount	125 °C	-55 °C

Catalog

Enhanced-product, six-bit inverting open-drain fixed-direction level translator

Key Features

• Wide operating range of 1.8V to 5.5VSingle-supply voltage translator (refer to LVxT Enhanced Input Voltage):Up translation:1.2V to 1.8V1.5V to 2.5 V1.8V to 3.3V3.3V to 5.0 VDown translation:5.0V, 3.3V, 2.5 V to 1.8V5.0V, 3.3V to 2.5V5.0V to 3.3V5.5V tolerant input pinsSupports standard pinoutsUp to 150Mbps with 5V or 3.3V VCCLatch-up performance exceeds 250mAper JESD 17Supports defense, aerospace, and medical applications:Controlled baselineOne assembly and test siteOne fabrication siteExtended product life cycleProduct traceabilityWide operating range of 1.8V to 5.5VSingle-supply voltage translator (refer to LVxT Enhanced Input Voltage):Up translation:1.2V to 1.8V1.5V to 2.5 V1.8V to 3.3V3.3V to 5.0 VDown translation:5.0V, 3.3V, 2.5 V to 1.8V5.0V, 3.3V to 2.5V5.0V to 3.3V5.5V tolerant input pinsSupports standard pinoutsUp to 150Mbps with 5V or 3.3V VCCLatch-up performance exceeds 250mAper JESD 17Supports defense, aerospace, and medical applications:Controlled baselineOne assembly and test siteOne fabrication siteExtended product life cycleProduct traceability

Description

The SN74LV6T06-EP device contains six independent inverters with open-drain outputs and extended voltage operation to allow for level translation. Each inverter performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output). The SN74LV6T06-EP device contains six independent inverters with open-drain outputs and extended voltage operation to allow for level translation. Each inverter performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.2V, 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).