SN74LV05A6-ch, 2-V to 5.5-V inverters with open-drain outputs | Gates and Inverters | 7 | Active | The SN74LV05A device contains six independent inverters designed for 2 V to 5.5 V VCCoperation.
This device performs the Boolean function Y =A.
The SN74LV05A device contains six independent inverters designed for 2 V to 5.5 V VCCoperation.
This device performs the Boolean function Y =A. |
SN74LV06A6-ch, 2-V to 5.5-V inverters with open-drain outputs | Logic | 7 | Active | These hex inverter buffers/drivers are designed for 2 V to 5.5 V VCCoperation.
The SN74LV06A device performs the Boolean function Y =Ain positive logic.
The open-drain output require pull-up resistors to perform correctly and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions.
These hex inverter buffers/drivers are designed for 2 V to 5.5 V VCCoperation.
The SN74LV06A device performs the Boolean function Y =Ain positive logic.
The open-drain output require pull-up resistors to perform correctly and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. |
SN74LV07A6-ch, 2-V to 5.5-V buffers with open-drain outputs | Logic | 10 | Active | These hex buffers/drivers are designed for 2-V to5.5-V VCCoperation.
The SN74LV07A device performs the Boolean function Y = A in positive logic.
These hex buffers/drivers are designed for 2-V to5.5-V VCCoperation.
The SN74LV07A device performs the Boolean function Y = A in positive logic. |
SN74LV08A-EP4-ch, 2-input 2-V to 5.5-V high-speed (7 ns) AND gate | Gates and Inverters | 11 | Active | This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCCoperation.
The SN74LV08A-EP performs the Boolean function Y = A • B or Y = (A\ + B\)\ in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCCoperation.
The SN74LV08A-EP performs the Boolean function Y = A • B or Y = (A\ + B\)\ in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LV10A3-ch, 3-input, 2-V to 5.5-V NAND gates | Gates and Inverters | 11 | Active | These triple 3-input positive-NAND gates are designed for 2 V to 5.5 V VCCoperation. The SN74LV10A devices perform the Boolean function Y =A • B • Cin positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
These triple 3-input positive-NAND gates are designed for 2 V to 5.5 V VCCoperation. The SN74LV10A devices perform the Boolean function Y =A • B • Cin positive logic. These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. |
SN74LV11A-Q1Enhanced product, 3-ch, 3-input 2-V to 5.5-V high-speed (7 ns) AND gate | Integrated Circuits (ICs) | 9 | Active | These triple 3-input positive-AND gates are designed for 2-V to 5.5-V V CC operation.
The SN74LV11A-Q1 devices perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic.
These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
These triple 3-input positive-AND gates are designed for 2-V to 5.5-V V CC operation.
The SN74LV11A-Q1 devices perform the Boolean function Y = A • B • C or Y = A + B + C in positive logic.
These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LV123A-Q1Automotive Catalog Dual Retriggerable Monostable Multivibrators | Integrated Circuits (ICs) | 10 | Active | The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCCoperation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A\ input is low, and the B input goes high. In the second method, the B input is high, and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR)\ input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cextand Rext/Cext(positive) and an external resistor connected between Rext/Cextand VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cextand VCC. The output pulse duration also can be reduced by taking CLR\ low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A\, B, and CLR\ inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A)\ or high-level-active (B) input. Pulse duration can be reduced by taking CLR\ low. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.
During power up, Q outputs are in the low state, and Q\ outputs are in the high state. The outputs are glitch free, without applying a reset pulse.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V VCCoperation.
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, the A\ input is low, and the B input goes high. In the second method, the B input is high, and the A\ input goes low. In the third method, the A\ input is low, the B input is high, and the clear (CLR)\ input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cextand Rext/Cext(positive) and an external resistor connected between Rext/Cextand VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cextand VCC. The output pulse duration also can be reduced by taking CLR\ low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A\, B, and CLR\ inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A)\ or high-level-active (B) input. Pulse duration can be reduced by taking CLR\ low. The input/output timing diagram illustrates pulse control by retriggering the inputs and early clearing.
During power up, Q outputs are in the low state, and Q\ outputs are in the high state. The outputs are glitch free, without applying a reset pulse.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LV125A4-ch, 2-V to 5.5-V buffers with 3-state outputs | Logic | 27 | Active | The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCCoperation.
The SN74LV125A quadruple bus buffer gate is designed for 2-V to 5.5-V VCCoperation. |
SN74LV126A4-ch, 2-V to 5.5-V buffers with 3-state outputs | Integrated Circuits (ICs) | 7 | Active | The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.
These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.
The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.
These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.
The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. |
SN74LV132A4-ch, 4-input, 2-V to 5.5-V NAND gates with Schmitt-Trigger inputs | Logic | 9 | Active | The ’LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCCoperation.
The ’LV132A devices perform the Boolean function Y =A • Bor Y =A+Bin positive logic.
Each circuit functions as a NAND gate, but because of the Schmitt trigger, it has different input threshold levels for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
The ’LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCCoperation.
The ’LV132A devices perform the Boolean function Y =A • Bor Y =A+Bin positive logic.
Each circuit functions as a NAND gate, but because of the Schmitt trigger, it has different input threshold levels for positive- and negative-going signals.
These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals. |
