SN74LV126A Series

4-ch, 2-V to 5.5-V buffers with 3-state outputs

Catalog

4-ch, 2-V to 5.5-V buffers with 3-state outputs

Part	Number of Bits per Element	Mounting Type	Package / Case [custom]	Package / Case [custom]	Package / Case	Operating Temperature [Min]	Operating Temperature [Max]	Logic Type	Supplier Device Package	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Elements	Output Type	Package / Case	Package / Case	Package / Case [x]	Package / Case [y]
Texas Instruments SN74LV126APWR	1	Surface Mount	0.173 "	4.4 mm	14-TSSOP	-40 °C	125 °C	Buffer Non-Inverting	14-TSSOP	5.5 V	2 V	16 mA	16 mA	4	3-State
Texas Instruments SN74LV126ADBR	1	Surface Mount			14-SSOP	-40 °C	125 °C	Buffer Non-Inverting	14-SSOP	5.5 V	2 V	16 mA	16 mA	4	3-State	5.3 mm	0.209 "
Texas Instruments SN74LV126ADGVR	1	Surface Mount			14-TFSOP	-40 °C	125 °C	Buffer Non-Inverting		5.5 V	2 V	16 mA	16 mA	4	3-State			0.173 in 4.4 mm
Texas Instruments SN74LV126AD	1	Surface Mount			14-SOIC	-40 °C	125 °C	Buffer Non-Inverting		5.5 V	2 V	16 mA	16 mA	4	3-State			0.154 in	3.9 mm
Texas Instruments SN74LV126APWRG4	1	Surface Mount	0.173 "	4.4 mm	14-TSSOP	-40 °C	125 °C	Buffer Non-Inverting	14-TSSOP	5.5 V	2 V	16 mA	16 mA	4	3-State
Texas Instruments SN74LV126ANSR	1	Surface Mount			14-SOIC	-40 °C	125 °C	Buffer Non-Inverting	14-SO	5.5 V	2 V	16 mA	16 mA	4	3-State			0.209 "	5.3 mm
Texas Instruments SN74LV126ADR	1	Surface Mount			14-SOIC	-40 °C	125 °C	Buffer Non-Inverting		5.5 V	2 V	16 mA	16 mA	4	3-State			0.154 in	3.9 mm

Catalog

4-ch, 2-V to 5.5-V buffers with 3-state outputs

Key Features

• 2V to 5.5V VCC operationMaximum tpd of 6.5ns at 5VTypical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°CTypical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°CIoff supports live insertion, partial power down mode, and back drive protectionSupport mixed-mode voltage operation on all portsLatch-up performance exceeds 250mAper JESD 172V to 5.5V VCC operationMaximum tpd of 6.5ns at 5VTypical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°CTypical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°CIoff supports live insertion, partial power down mode, and back drive protectionSupport mixed-mode voltage operation on all portsLatch-up performance exceeds 250mAper JESD 17

Description

The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation. These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation. The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation. These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation. The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.