Texas Instruments

The SN74LV164A-Q1 devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCCoperation. The SN74LV164A-Q1 devices are 8-bit parallel-out serial shift registers designed for 2-V to 5.5-V VCCoperation.

The SN74LV165A device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V VCCoperation. When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output,QH. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The SN74LV165A device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V VCCoperation. When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output,QH. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The SN74LV165B-EP device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V V CC operation. When the device is clocked, data is shifted toward the serial output Q H. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SN74LV165B-EP devices features a clock-inhibit function and a complemented serial output, Q H. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The SN74LV165B-EP device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V V CC operation. When the device is clocked, data is shifted toward the serial output Q H. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The SN74LV165B-EP devices features a clock-inhibit function and a complemented serial output, Q H. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2 V to 5.5 V VCCoperation. The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2 V to 5.5 V VCCoperation.

The SN74LV175A device is quadruple D-type flip-flops designed for 2 V to 5.5 V V CC operation. These devices have a direct clear ( CLR) input and feature complementary outputs from each flip-flop. The SN74LV175A device is quadruple D-type flip-flops designed for 2 V to 5.5 V V CC operation. These devices have a direct clear ( CLR) input and feature complementary outputs from each flip-flop.

SN74LV1T00 is a low voltage CMOS gate logic that operates at a wider voltage range for industrial, portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8V/2.5V/3.3V/5V CMOS levels The input is designed with a lower threshold circuit to match 1.8V input logic at VCC = 3.3V and can be used in 1.8V to 3.3V level up translation. In addition, the 5V tolerant input pins enable down translation (e.g. 3.3V to 2.5V output at VCC = 2.5V). The wide VCC range of 1.8V to 5.5V allows generation of desired output levels to connect to controllers or processors. The SN74LV1T00 is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs. SN74LV1T00 is a low voltage CMOS gate logic that operates at a wider voltage range for industrial, portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8V/2.5V/3.3V/5V CMOS levels The input is designed with a lower threshold circuit to match 1.8V input logic at VCC = 3.3V and can be used in 1.8V to 3.3V level up translation. In addition, the 5V tolerant input pins enable down translation (e.g. 3.3V to 2.5V output at VCC = 2.5V). The wide VCC range of 1.8V to 5.5V allows generation of desired output levels to connect to controllers or processors. The SN74LV1T00 is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

The SN74LV1T00-Q1 is a 2-input NAND Gate. Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3V to 2.5V output). The SN74LV1T00-Q1 is a 2-input NAND Gate. Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The SN74LV1T02 is a single 2-input NOR gate with reduced input thresholds to support voltage translation applications. The SN74LV1T02 is a single 2-input NOR gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T02-Q1 is a 2-input NOR Gate. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output). The SN74LV1T02-Q1 is a 2-input NOR Gate. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The SN74LV1T04 is a single NOT gate with reduced input thresholds to support voltage translation applications. The SN74LV1T04 is a single NOT gate with reduced input thresholds to support voltage translation applications.