SN74LV138A-Q1Automotive three-line to eight-line decoders/demultiplexers | Signal Switches, Multiplexers, Decoders | 1 | Active | The SN74LV138A-Q1 device is 3-line to 8-line decoders/demultiplexers designed for 2 V to 5.5 V VCCoperation.
The conditions at the binary-select inputs (A0, A1, A2) and the three enable inputs (G2,G0,G1) select one of eight output lines. The two active-low (G0,G1) and one active-high (G2) enable inputs reduce the need for external gates or inverters when expanding.
The SN74LV138A-Q1 device is 3-line to 8-line decoders/demultiplexers designed for 2 V to 5.5 V VCCoperation.
The conditions at the binary-select inputs (A0, A1, A2) and the three enable inputs (G2,G0,G1) select one of eight output lines. The two active-low (G0,G1) and one active-high (G2) enable inputs reduce the need for external gates or inverters when expanding. |
SN74LV138ATThree-line to eight-line decoders/demultiplexers | Integrated Circuits (ICs) | 19 | Active | The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1,G2A,G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
This device is fully specified for partial-power-down application susing Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1,G2A,G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
This device is fully specified for partial-power-down application susing Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LV139ADual 2-Line To 4-Line Decoders/Demultiplexers | Logic | 7 | Active | The SN74LV139A devices are dual 2-line to 4-line decoders/demultiplexers designed for 2V to 5.5V VCC operation.
The SN74LV139A devices are dual 2-line to 4-line decoders/demultiplexers designed for 2V to 5.5V VCC operation. |
SN74LV14A-EPEnhanced product 6-ch, 2-V to 5.5-V inverters with Schmitt-Trigger inputs | Logic | 13 | Active | This hex Schmitt-trigger inverter is designed for 2-V to 5.5-V VCCoperation.
The SN74LV14A contains six independent inverters. This device performs the Boolean function Y =A.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This hex Schmitt-trigger inverter is designed for 2-V to 5.5-V VCCoperation.
The SN74LV14A contains six independent inverters. This device performs the Boolean function Y =A.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LV14B-EPEnhanced product six-channel 2-V to 5.5-V inverters with Schmitt-Trigger inputs | Integrated Circuits (ICs) | 1 | Active | The SN74LV14B-EP device contains six independent Inverter with Schmitt-trigger inputs designed for 2 V to 5.5 V V CC operation. Each gate performs the Boolean function Y = A in positive logic.
This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The SN74LV14B-EP device contains six independent Inverter with Schmitt-trigger inputs designed for 2 V to 5.5 V V CC operation. Each gate performs the Boolean function Y = A in positive logic.
This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. |
| Integrated Circuits (ICs) | 1 | Obsolete | |
| Logic | 3 | Active | The SN74LV161284 is designed for 4.5-V to 5.5-V VCCoperation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-kintegrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCCCABLE. If VCCCABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCCis designed for 4.5-V to 5.5-V operation. VCCCABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.
The SN74LV161284 is designed for 4.5-V to 5.5-V VCCoperation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-kintegrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCCCABLE. If VCCCABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCCis designed for 4.5-V to 5.5-V operation. VCCCABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation. |
| Integrated Circuits (ICs) | 8 | Active | The ’LV161A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCCoperation.
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV161A devices is asynchronous. A low level at the clear (CLR)\ input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD)\, or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The ’LV161A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCCoperation.
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV161A devices is asynchronous. A low level at the clear (CLR)\ input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD)\, or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD\) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times.
These devices are fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. |
| Integrated Circuits (ICs) | 8 | Active | The ’LV163A devices are 4-bit synchronous binary counters designed for 2V to 5.5V VCC operation.
The ’LV163A devices are 4-bit synchronous binary counters designed for 2V to 5.5V VCC operation. |
SN74LV164AEight-bit parallel-out serial shift registers | Logic | 9 | Active | The SN74LV164A devices are 8-bit parallel-out serial shift registers designed for 2 V to 5.5 V V CC operation.
The SN74LV164A devices are 8-bit parallel-out serial shift registers designed for 2 V to 5.5 V V CC operation. |
