Texas Instruments

OMAP3530 and OMAP3525 devices are based on the enhanced OMAP 3 architecture. The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: The device supports high-level operating systems (HLOSs), such as: This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device: The device also offers: OMAP3530 and OMAP3525 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences). This data manual presents the electrical and mechanical specifications for the OMAP3530 and OMAP3525 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP3530 and OMAP3525 applications processors unless otherwise indicated. This data manual consists of the following sections: OMAP3530 and OMAP3525 devices are based on the enhanced OMAP 3 architecture. The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: The device supports high-level operating systems (HLOSs), such as: This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device: The device also offers: OMAP3530 and OMAP3525 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences). This data manual presents the electrical and mechanical specifications for the OMAP3530 and OMAP3525 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP3530 and OMAP3525 applications processors unless otherwise indicated. This data manual consists of the following sections:

The OMAP5910 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a TMS320C55x DSP core and a high-performance TI925T ARM core. The OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as well as the Texas Instruments (TI) DSP/BIOS™ software kernel foundation, and is available in a 289-ball MicroStar BGA package. The OMAP5910 is targeted at the following applications: The OMAP5910 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and RISC technologies, incorporating a TMS320C55x DSP core and a high-performance TI925T ARM core. The OMAP5910 device is designed to run leading open and embedded RISC-based operating systems, as well as the Texas Instruments (TI) DSP/BIOS™ software kernel foundation, and is available in a 289-ball MicroStar BGA package. The OMAP5910 is targeted at the following applications:

OMAP5912 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and reduced instruction set computer (RISC)technologies, incorporating a TMS320C55x DSP core and a high-performance ARM926EJ-S ARM® core. OMAP5912 is a highly integrated hardware and software platform, designed to meet the application processing needs of next-generation embedded devices. The OMAP™ platform enables OEMs and ODMs to quickly bring to market devices featuring rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture provides benefits of both DSP and reduced instruction set computer (RISC)technologies, incorporating a TMS320C55x DSP core and a high-performance ARM926EJ-S ARM® core.

The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs. The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and data and program Memory Management Units (MMUs) with table look-aside buffers. The ARM core has separate 16-KB instruction and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM. The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance. The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with bothRTSandCTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution. The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs. The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and data and program Memory Management Units (MMUs) with table look-aside buffers. The ARM core has separate 16-KB instruction and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM. The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance. The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with bothRTSandCTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The OMAPL138B C6-Integra™ DSP+ARM® processor is a low-power applications processor based on an ARM926EJ-S™ and a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM. The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance. For security enabled devices, TI’s Basic Secure Boot allows users to protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based "root-of-trust", the secure boot flow guarantees a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks but can be enabled during the secure boot process during application development. The boot modules themselves are encrypted while sitting in external non-volatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. This protects the users’ IP and enables them to securely set up the system and begin device operation with known, trusted code. Basic Secure Boot utilizes either SHA-1 or SHA-256, and AES-128 for boot image validation. It also uses AES-128 for boot image encryption. The secure boot flow employs a multi-layer encryption scheme which not only protects the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect user encryption keys. When an update is needed, the customer creates a new encrypted image using its encryption keys. Then the device can acquire the image via an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, refer to theTMS320C674x/OMAP-L1x Processor Security User’s Guide(SPRUGQ9). The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C) Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each withRTSandCTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces. The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps). The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on each of two channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE and WAIT signals to provide control for a variety of data converters. A Video Port Interface (VPIF) is included providing a flexible video input/output port. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The device has a complete set of development tools for the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. The OMAPL138B C6-Integra™ DSP+ARM® processor is a low-power applications processor based on an ARM926EJ-S™ and a C674x DSP core. It provides significantly lower power than other members of the TMS320C6000™ platform of DSPs. The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM. The device DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance. For security enabled devices, TI’s Basic Secure Boot allows users to protect proprietary intellectual property and prevents external entities from modifying user-developed algorithms. By starting from a hardware-based "root-of-trust", the secure boot flow guarantees a known good starting point for code execution. By default, the JTAG port is locked down to prevent emulation and debug attacks but can be enabled during the secure boot process during application development. The boot modules themselves are encrypted while sitting in external non-volatile memory, such as flash or EEPROM, and are decrypted and authenticated when loaded during secure boot. This protects the users’ IP and enables them to securely set up the system and begin device operation with known, trusted code. Basic Secure Boot utilizes either SHA-1 or SHA-256, and AES-128 for boot image validation. It also uses AES-128 for boot image encryption. The secure boot flow employs a multi-layer encryption scheme which not only protects the boot process but offers the ability to securely upgrade boot and application software code. A 128-bit device-specific cipher key, known only to the device and generated using a NIST-800-22 certified random number generator, is used to protect user encryption keys. When an update is needed, the customer creates a new encrypted image using its encryption keys. Then the device can acquire the image via an external interface, such as Ethernet, and overwrite the existing code. For more details on the supported security features or TI’s Basic Secure Boot, refer to theTMS320C674x/OMAP-L1x Processor Security User’s Guide(SPRUGQ9). The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; one USB2.0 OTG interface; one USB1.1 OHCI interface; two inter-integrated circuit (I2C) Bus interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSP) with FIFO buffers; two SPI interfaces with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI) ; up to 9 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; three UART interfaces (each withRTSandCTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed DDR2/Mobile DDR controller. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and a network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration. The EMAC supports both MII and RMII interfaces. The SATA controller provides a high-speed interface to mass data storage devices. The SATA controller supports both SATA I (1.5 Gbps) and SATA II (3.0 Gbps). The Universal Parallel Port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The UPP supports programmable data widths between 8- to 16-bits on each of two channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE and WAIT signals to provide control for a variety of data converters. A Video Port Interface (VPIF) is included providing a flexible video input/output port. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The device has a complete set of development tools for the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The ONET1101L is a high-speed, 3.3-V laser driver designed to directly modulate a laser at data rates from 2 Gbps to 11.3 Gbps. The device provides a two-wire serial interface that helps digital control of the modulation, plus bias currents and cross point, eliminating the need for external components. An optional input equalizer can be used for equalization of up to 300 mm (12") of microstrip or stripline transmission line on FR4 printed circuit boards. The ONET1101L includes an integrated automatic power control (APC) loop, plus circuitry to support laser safety and transceiver management systems. The laser driver is characterized for operation from -25°C to 100°C case temperature and is available in a small footprint using a 4mm × 4mm, 24-pin RoHS-compliant QFN package. The ONET1101L is a high-speed, 3.3-V laser driver designed to directly modulate a laser at data rates from 2 Gbps to 11.3 Gbps. The device provides a two-wire serial interface that helps digital control of the modulation, plus bias currents and cross point, eliminating the need for external components. An optional input equalizer can be used for equalization of up to 300 mm (12") of microstrip or stripline transmission line on FR4 printed circuit boards. The ONET1101L includes an integrated automatic power control (APC) loop, plus circuitry to support laser safety and transceiver management systems. The laser driver is characterized for operation from -25°C to 100°C case temperature and is available in a small footprint using a 4mm × 4mm, 24-pin RoHS-compliant QFN package.

The ONET1130EC is a 2.5 V integrated modulator driver and limiting amplifier with transmit and receive clock and data recovery (CDR) designed to operate between 9.80 Gbps and 11.7 Gbps without the need for a reference clock. Optical and electrical loopback are included. CDR bypass mode can be used for operation at lower data rates and a two-wire serial interface allows digital control of the features. The transmit path consists of an adjustable input equalizer for equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line of FR4 printed circuit boards, a multi-rate CDR and an output modulator driver. Output waveform control, in the form of cross-point adjustment and de-emphasis are available to improve the optical eye mask margin. Bias current for the laser is provided and an integrated automatic power control (APC) loop to compensate for variations in average optical power over voltage, temperature and time is included. The receive path consists of a limiting amplifier with programmable equalization and threshold adjustment, a multi-rate CDR and output de-emphasis to compensate for frequency dependent loss of connectors, microstrips or striplines connected to the output of the device, The receiver output amplitude and loss of signal assert level can be adjusted. The ONET1130EC contains internal analog to digital and digital to analog converters to support transceiver management and eliminate the need for special purpose microcontrollers. The transceiver is characterized for operation from –40°C to 100°C case temperatures and is available in a small footprint 4mm × 4mm, 32 pin RoHS compliant VQFN package. The ONET1130EC is a 2.5 V integrated modulator driver and limiting amplifier with transmit and receive clock and data recovery (CDR) designed to operate between 9.80 Gbps and 11.7 Gbps without the need for a reference clock. Optical and electrical loopback are included. CDR bypass mode can be used for operation at lower data rates and a two-wire serial interface allows digital control of the features. The transmit path consists of an adjustable input equalizer for equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line of FR4 printed circuit boards, a multi-rate CDR and an output modulator driver. Output waveform control, in the form of cross-point adjustment and de-emphasis are available to improve the optical eye mask margin. Bias current for the laser is provided and an integrated automatic power control (APC) loop to compensate for variations in average optical power over voltage, temperature and time is included. The receive path consists of a limiting amplifier with programmable equalization and threshold adjustment, a multi-rate CDR and output de-emphasis to compensate for frequency dependent loss of connectors, microstrips or striplines connected to the output of the device, The receiver output amplitude and loss of signal assert level can be adjusted. The ONET1130EC contains internal analog to digital and digital to analog converters to support transceiver management and eliminate the need for special purpose microcontrollers. The transceiver is characterized for operation from –40°C to 100°C case temperatures and is available in a small footprint 4mm × 4mm, 32 pin RoHS compliant VQFN package.

The ONET1131EC is a 2.5-V EML modulator driver with transmit clock and data recovery (CDR) designed to operate between 9.8 Gbps and 11.7 Gbps without the need for a reference clock. CDR bypass mode can be used for operation at lower data rates and a two-wire serial interface allows digital control of features like output polarity select and input equalization. The transmit path consists of an adjustable input equalizer for equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line of FR4 printed circuit boards, a multi-rate CDR and an output modulator driver. Output waveform control, in the form of cross-point adjustment and de-emphasis, is available to improve the optical eye mask margin. The device provides bias current for the laser and an integrated automatic power control (APC) loop to compensate for variations in average optical power over voltage, temperature and time. The ONET1131EC contains internal analog to digital and digital to analog converters to support transceiver management and eliminate the need for special purpose microcontrollers. The ONET1131EC is a 2.5-V EML modulator driver with transmit clock and data recovery (CDR) designed to operate between 9.8 Gbps and 11.7 Gbps without the need for a reference clock. CDR bypass mode can be used for operation at lower data rates and a two-wire serial interface allows digital control of features like output polarity select and input equalization. The transmit path consists of an adjustable input equalizer for equalization of up to 300 mm (12 inches) of microstrip or stripline transmission line of FR4 printed circuit boards, a multi-rate CDR and an output modulator driver. Output waveform control, in the form of cross-point adjustment and de-emphasis, is available to improve the optical eye mask margin. The device provides bias current for the laser and an integrated automatic power control (APC) loop to compensate for variations in average optical power over voltage, temperature and time. The ONET1131EC contains internal analog to digital and digital to analog converters to support transceiver management and eliminate the need for special purpose microcontrollers.