| Integrated Circuits (ICs) | 1 | Obsolete | |
NE5532ADual, 30-V, 10-MHz, low-noise (6 nV/√Hz) operational amplifier for audio applications | Amplifiers | 12 | Active | The NE5532, NE5532A, SA5532, and SA5532A devices are high-performance operational amplifiers combining excellent DC and AC characteristics. They feature very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, high slew rate, input-protection diodes, and output short-circuit protection. These operational amplifiers are compensated internally for unity-gain operation. These devices have specified maximum limits for equivalent input noise voltage.
The NE5532, NE5532A, SA5532, and SA5532A devices are high-performance operational amplifiers combining excellent DC and AC characteristics. They feature very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, high slew rate, input-protection diodes, and output short-circuit protection. These operational amplifiers are compensated internally for unity-gain operation. These devices have specified maximum limits for equivalent input noise voltage. |
NE5534ASingle, 30-V, 10-MHz, low-noise (6 nV/√Hz) operational amplifier for audio applications | Amplifiers | 10 | Active | The NE5534, NE5534A, SA5534, and SA5534A devices are high-performance operational amplifiers combining excellent dc and ac characteristics. Some of the features include very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, and high slew rate.
These operational amplifiers are compensated internally for a gain equal to or greater than three. Optimization of the frequency response for various applications can be obtained by use of an external compensation capacitor between COMP and COMP/BAL. The devices feature input-protection diodes, output short-circuit protection, and offset-voltage nulling capability with use of the BALANCE and COMP/BAL pins.
For the NE5534A and SA5534A devices, a maximum limit is specified for the equivalent input noise voltage.
The NE5534, NE5534A, SA5534, and SA5534A devices are high-performance operational amplifiers combining excellent dc and ac characteristics. Some of the features include very low noise, high output-drive capability, high unity-gain and maximum-output-swing bandwidths, low distortion, and high slew rate.
These operational amplifiers are compensated internally for a gain equal to or greater than three. Optimization of the frequency response for various applications can be obtained by use of an external compensation capacitor between COMP and COMP/BAL. The devices feature input-protection diodes, output short-circuit protection, and offset-voltage nulling capability with use of the BALANCE and COMP/BAL pins.
For the NE5534A and SA5534A devices, a maximum limit is specified for the equivalent input noise voltage. |
NE555Single Precision Timer | Programmable Timers and Oscillators | 12 | Active | The Nx555 and Sx555 devices are precision timing circuits capable of producing accurate time delays or oscillation. In time-delay or monostable operating modes, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle are controlled independently with two external resistors and a single external capacitor.
Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering
The output circuit is capable of sinking or sourcing current up to 200mA. Operation is specified for supplies of 5V to 15V. With a 5V supply, output levels are compatible with TTL inputs.
The Nx555 and Sx555 devices are precision timing circuits capable of producing accurate time delays or oscillation. In time-delay or monostable operating modes, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle are controlled independently with two external resistors and a single external capacitor.
Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering
The output circuit is capable of sinking or sourcing current up to 200mA. Operation is specified for supplies of 5V to 15V. With a 5V supply, output levels are compatible with TTL inputs. |
NE556Dual precision timer | Programmable Timers and Oscillators | 9 | Active | The Nx556 and Sx556 devices provide two independent timing circuits of the NA555, NE555, SA555, or SE555 type in each package. These circuits operate in an astable or monostable mode with external resistor-capacitor (RC) timing control. The basic timing provided by the RC time constant is controlled actively by modulating the bias of the control-voltage input.
Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering.
The Nx556 and Sx556 devices provide two independent timing circuits of the NA555, NE555, SA555, or SE555 type in each package. These circuits operate in an astable or monostable mode with external resistor-capacitor (RC) timing control. The basic timing provided by the RC time constant is controlled actively by modulating the bias of the control-voltage input.
Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering. |
| Interface | 1 | Obsolete | |
| Evaluation Boards | 1 | Active | |
| Data Acquisition | 1 | Active | The NN325 device is an ultra-low-power multisensing touch manager that includes optimized peripherals dedicated for high-performance touch-sensing applications. The device is optimized for ultra-low power operation using five low-power modes. The embedded powerful 16-bit RISC core based on a MSP430 architecture offers 16-bit registers and constant generators to achieve maximum code efficiency. The digitally controlled oscillator (DCO) allows wakeup from low-power modes to active mode in less than 1 µs. The ultra-low-power core comes together with two built-in 16-bit timers, a universal serial communication interface (USCI), a 10-bit ADC with integrated reference and data transfer controller (DTC), and 32 I/O pins.
The NN325 device is an ultra-low-power multisensing touch manager that includes optimized peripherals dedicated for high-performance touch-sensing applications. The device is optimized for ultra-low power operation using five low-power modes. The embedded powerful 16-bit RISC core based on a MSP430 architecture offers 16-bit registers and constant generators to achieve maximum code efficiency. The digitally controlled oscillator (DCO) allows wakeup from low-power modes to active mode in less than 1 µs. The ultra-low-power core comes together with two built-in 16-bit timers, a universal serial communication interface (USCI), a 10-bit ADC with integrated reference and data transfer controller (DTC), and 32 I/O pins. |
| UARTs (Universal Asynchronous Receiver Transmitter) | 2 | Obsolete | |
NS16C2552Dual UART with 16-byte FIFO and up to 5 Mbit/s Data Rate | Interface | 2 | Active | The NS16C2552 and NS16C2752 are dual channel Universal Asynchronous Receiver/Transmitter (DUART). The footprint and the functions are compatible to the PC16552D, while new features are added to the UART device. These features include low voltage support, 5V tolerant inputs, enhanced features, enhanced register set, and higher data rate.
The two serial channels are completely independent of each other, except for a common CPU interface and crystal input. On power-up both channels are functionally identical to the PC16552D. Each channel can operate with on-chip transmitter and receiver FIFO’s (in FIFO mode).
In the FIFO mode each channel is capable of buffering 16 bytes (for NS16C2552) or 64 bytes (for NS16C2752) of data in both the transmitter and receiver. The receiver FIFO also has additional 3 bits of error data per location. All FIFO control logic is on-chip to minimize system software overhead and maximize system efficiency.
To improve the CPU processing bandwidth, the data transfers between the DUART and the CPU can be done using DMA controller. Signaling for DMA transfers is done through two pins per channel (TXRDYandRXRDY). TheRXRDYfunction is multiplexed on one pin with theOUT2and BAUDOUT functions. The configuration is through Alternate Function Register.
The fundamental function of the UART is converting between parallel and serial data. Serial-to-parallel conversion is done on the UART receiver and parallel-to-serial conversion is done on the transmitter. The CPU can read the complete status of each channel at any time. Status information reported includes the type and condition of the transfer operations being performed by the DUART, as well as any error conditions (parity, overrun, framing, or break interrupt).
The NS16C2552 and NS16C2752 include one programmable baud rate generator for each channel. Each baud rate generator is capable of dividing the clock input by divisors of 1 to (216- 1), and producing a 16X clock for driving the internal transmitter logic and for receiver sampling circuitry. The NS16C2552 and NS16C2752 have complete MODEM-control capability, and a processor-interrupt system. The interrupts can be programmed by the user to minimize the processing required to handle the communications link.
The NS16C2552 and NS16C2752 are dual channel Universal Asynchronous Receiver/Transmitter (DUART). The footprint and the functions are compatible to the PC16552D, while new features are added to the UART device. These features include low voltage support, 5V tolerant inputs, enhanced features, enhanced register set, and higher data rate.
The two serial channels are completely independent of each other, except for a common CPU interface and crystal input. On power-up both channels are functionally identical to the PC16552D. Each channel can operate with on-chip transmitter and receiver FIFO’s (in FIFO mode).
In the FIFO mode each channel is capable of buffering 16 bytes (for NS16C2552) or 64 bytes (for NS16C2752) of data in both the transmitter and receiver. The receiver FIFO also has additional 3 bits of error data per location. All FIFO control logic is on-chip to minimize system software overhead and maximize system efficiency.
To improve the CPU processing bandwidth, the data transfers between the DUART and the CPU can be done using DMA controller. Signaling for DMA transfers is done through two pins per channel (TXRDYandRXRDY). TheRXRDYfunction is multiplexed on one pin with theOUT2and BAUDOUT functions. The configuration is through Alternate Function Register.
The fundamental function of the UART is converting between parallel and serial data. Serial-to-parallel conversion is done on the UART receiver and parallel-to-serial conversion is done on the transmitter. The CPU can read the complete status of each channel at any time. Status information reported includes the type and condition of the transfer operations being performed by the DUART, as well as any error conditions (parity, overrun, framing, or break interrupt).
The NS16C2552 and NS16C2752 include one programmable baud rate generator for each channel. Each baud rate generator is capable of dividing the clock input by divisors of 1 to (216- 1), and producing a 16X clock for driving the internal transmitter logic and for receiver sampling circuitry. The NS16C2552 and NS16C2752 have complete MODEM-control capability, and a processor-interrupt system. The interrupts can be programmed by the user to minimize the processing required to handle the communications link. |
