OMAP3530 Series

Applications Processor

Catalog

Applications Processor

Part	Co-Processors/DSP	RAM Controllers	USB	Core Processor	Additional Interfaces	Mounting Type	Voltage - I/O	Package / Case	Speed	Display & Interface Controllers	Number of Cores/Bus Width	Operating Temperature [custom]	Supplier Device Package	Operating Temperature [Min]	Operating Temperature [Max]
Texas Instruments OMAP3530ECBBAR	C64x+ Multimedia NEON™ SIMD Signal Processing	LPDDR	USB 1.x (3) USB 2.0 (1)	ARM® Cortex®-A8	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	Surface Mount	1.8 V 3 V	515-VFBGA FCBGA	600 MHz	LCD	1 Core 32 Bit	-40 °C 105 °C	515-POP-FCBGA (12x12)
Texas Instruments OMAP3530ECUS72	C64x+ Multimedia NEON™ SIMD Signal Processing	LPDDR	USB 1.x (3) USB 2.0 (1)	ARM® Cortex®-A8	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	Surface Mount	1.8 V 3 V	423-LFBGA FCBGA	720 MHz	LCD	1 Core 32 Bit		423-FCBGA (16x16)	0 °C	90 °C
Texas Instruments OMAP3530ECBBLPD	C64x+ Multimedia NEON™ SIMD Signal Processing	LPDDR	USB 1.x (3) USB 2.0 (1)	ARM® Cortex®-A8	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	Surface Mount	1.8 V 3 V	515-VFBGA FCBGA	600 MHz	LCD	1 Core 32 Bit		515-POP-FCBGA (12x12)	0 °C	90 °C
Texas Instruments OMAP3530ECBB72	C64x+ Multimedia NEON™ SIMD Signal Processing	LPDDR	USB 1.x (3) USB 2.0 (1)	ARM® Cortex®-A8	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	Surface Mount	1.8 V 3 V	515-VFBGA FCBGA	720 MHz	LCD	1 Core 32 Bit		515-POP-FCBGA (12x12)	0 °C	90 °C
Texas Instruments OMAP3530ECUSA	C64x+ Multimedia NEON™ SIMD Signal Processing	LPDDR	USB 1.x (3) USB 2.0 (1)	ARM® Cortex®-A8	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	Surface Mount	1.8 V 3 V	423-LFBGA FCBGA	600 MHz	LCD	1 Core 32 Bit	-40 °C 105 °C	423-FCBGA (16x16)
Texas Instruments OMAP3530ECBB	C64x+ Multimedia NEON™ SIMD Signal Processing	LPDDR	USB 1.x (3) USB 2.0 (1)	ARM® Cortex®-A8	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	Surface Mount	1.8 V 3 V	515-VFBGA FCBGA	600 MHz	LCD	1 Core 32 Bit		515-POP-FCBGA (12x12)	0 °C	90 °C
Texas Instruments OMAP3530ECBBALPD	C64x+ Multimedia NEON™ SIMD Signal Processing	LPDDR	USB 1.x (3) USB 2.0 (1)	ARM® Cortex®-A8	HDQ/1-Wire I2C McBSP McSPI MMC/SD/SDIO UART	Surface Mount	1.8 V 3 V	515-VFBGA FCBGA	600 MHz	LCD	1 Core 32 Bit	-40 °C 105 °C	515-POP-FCBGA (12x12)

Catalog

Applications Processor

Key Features

• OMAP3530 and OMAP3525 Devices:OMAP™ 3 ArchitectureMPU SubsystemUp to 720-MHz ARM® Cortex™-A8 CoreNEON™ SIMD CoprocessorHigh-Performance Image, Video, Audio (IVA2.2™) Accelerator SubsystemUp to 520-MHz TMS320C64x+™ DSP CoreEnhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)Video Hardware AcceleratorsPowerVR® SGX™ Graphics Accelerator (OMAP3530 Device Only)Tile-Based Architecture Delivering up to 10 MPoly/secUniversal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader FunctionalityIndustry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0Fine-Grained Task Switching, Load Balancing, and Power ManagementProgrammable High-Quality Image Anti-AliasingFully Software-Compatible with C64x and ARM9™Commercial and Extended Temperature GradesAdvanced Very-Long-Instruction-Word (VLIW) TMS320C64x+ DSP CoreEight Highly Independent Functional UnitsSix ALUs (32- and 40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock CycleTwo Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock CycleLoad-Store Architecture with Nonaligned Support64 32-Bit General-Purpose RegistersInstruction Packing Reduces Code SizeAll Instructions ConditionalAdditional C64x+ EnhancementsProtected Mode OperationExceptions Support for Error Detection and Program RedirectionHardware Support for Modulo Loop OperationC64x+ L1 and L2 Memory Architecture32KB of L1P Program RAM and Cache (Direct Mapped)80KB of L1D Data RAM and Cache (2-Way Set-Associative)64KB of L2 Unified Mapped RAM and Cache (4-Way Set-Associative)32KB of L2 Shared SRAM and 16KB of L2 ROMC64x+ Instruction Set FeaturesByte-Addressable (8-, 16-, 32-, and 64-Bit Data)8-Bit Overflow ProtectionBit Field Extract, Set, ClearNormalization, Saturation, Bit-CountingCompact 16-Bit InstructionsAdditional Instructions to Support Complex MultipliesARM Cortex-A8 CoreARMv7 ArchitectureTrustZone®Thumb®-2MMU EnhancementsIn-Order, Dual-Issue, Superscalar Microprocessor CoreNEON Multimedia ArchitectureOver 2x Performance of ARMv6 SIMDSupports Both Integer and Floating-Point SIMDJazelle® RCT Execution Environment ArchitectureDynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return StackEmbedded Trace Macrocell (ETM) Support for Noninvasive DebugARM Cortex-A8 Memory Architecture:16-KB Instruction Cache (4-Way Set-Associative)16-KB Data Cache (4-Way Set-Associative)256-KB L2 Cache112KB of ROM64KB of Shared SRAMEndianess:ARM Instructions – Little EndianARM Data – ConfigurableDSP Instruction and Data - Little EndianExternal Memory Interfaces:SDRAM Controller (SDRC)16- and 32-Bit Memory Controller with 1GB of Total Address SpaceInterfaces to Low-Power Double Data Rate (LPDDR) SDRAMSDRAM Memory Scheduler (SMS) and Rotation EngineGeneral Purpose Memory Controller (GPMC)16-Bit-Wide Multiplexed Address and Data BusUp to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select PinGlueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAMFlexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)Camera Image Signal Processor (ISP)CCD and CMOS Imager InterfaceMemory Data InputBT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 InterfaceGlueless Interface to Common Video DecodersResize EngineResize Images From 1/4x to 4xSeparate Horizontal and Vertical ControlDisplay SubsystemParallel Digital OutputUp to 24-Bit RGBHD Maximum ResolutionSupports Up to 2 LCD PanelsSupport for Remote Frame Buffer Interface (RFBI) LCD Panels2 10-Bit Digital-to-Analog Converters (DACs) Supporting:Composite NTSC and PAL VideoLuma and Chroma Separate Video (S-Video)Rotation 90-, 180-, and 270-DegreesResize Images From 1/4x to 8xColor Space Converter8-Bit Alpha BlendingSerial Communication5 Multichannel Buffered Serial Ports (McBSPs)512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)5-KB Transmit and Receive Buffer (McBSP2)SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix OperationsDirect Interface to I2S and PCM Device and TDM Buses128-Channel Transmit and Receive ModeFour Master or Slave Multichannel Serial Port Interface (McSPI) PortsHigh-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)High-, Full-, and Low-Speed Multiport USB Host Subsystem12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial InterfaceSupports Transceiverless Link Logic (TLL)One HDQ™/1-Wire® InterfaceThree UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) ControllersRemovable Media Interfaces:Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)Comprehensive Power, Reset, and Clock ManagementSmartReflex™ TechnologyDynamic Voltage and Frequency Scaling (DVFS)Test InterfacesIEEE 1149.1 (JTAG) Boundary-Scan CompatibleETM InterfaceSerial Data Transport Interface (SDTI)12 32-Bit General-Purpose Timers2 32-Bit Watchdog Timers1 32-Bit 32-kHz Sync TimerUp to 188 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)65-nm CMOS TechnologiesPackage-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)Discrete Memory Interface (Not Available in CBC Package)Packages:515-pin s-PBGA Package (CBB Suffix),.5-mm Ball Pitch (Top), .4-mm Ball Pitch (Bottom)515-pin s-PBGA Package (CBC Suffix),.65-mm Ball Pitch (Top), .5-mm Ball Pitch (Bottom)423-pin s-PBGA Package (CUS Suffix),.65-mm Ball Pitch1.8-V I/O and 3.0-V (MMC1 Only),0.985-V to 1.35-V Adaptive Processor Core Voltage0.985-V to 1.35-V Adaptive Core Logic VoltageNote: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.OMAP3530 and OMAP3525 Devices:OMAP™ 3 ArchitectureMPU SubsystemUp to 720-MHz ARM® Cortex™-A8 CoreNEON™ SIMD CoprocessorHigh-Performance Image, Video, Audio (IVA2.2™) Accelerator SubsystemUp to 520-MHz TMS320C64x+™ DSP CoreEnhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)Video Hardware AcceleratorsPowerVR® SGX™ Graphics Accelerator (OMAP3530 Device Only)Tile-Based Architecture Delivering up to 10 MPoly/secUniversal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader FunctionalityIndustry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0Fine-Grained Task Switching, Load Balancing, and Power ManagementProgrammable High-Quality Image Anti-AliasingFully Software-Compatible with C64x and ARM9™Commercial and Extended Temperature GradesAdvanced Very-Long-Instruction-Word (VLIW) TMS320C64x+ DSP CoreEight Highly Independent Functional UnitsSix ALUs (32- and 40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock CycleTwo Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock CycleLoad-Store Architecture with Nonaligned Support64 32-Bit General-Purpose RegistersInstruction Packing Reduces Code SizeAll Instructions ConditionalAdditional C64x+ EnhancementsProtected Mode OperationExceptions Support for Error Detection and Program RedirectionHardware Support for Modulo Loop OperationC64x+ L1 and L2 Memory Architecture32KB of L1P Program RAM and Cache (Direct Mapped)80KB of L1D Data RAM and Cache (2-Way Set-Associative)64KB of L2 Unified Mapped RAM and Cache (4-Way Set-Associative)32KB of L2 Shared SRAM and 16KB of L2 ROMC64x+ Instruction Set FeaturesByte-Addressable (8-, 16-, 32-, and 64-Bit Data)8-Bit Overflow ProtectionBit Field Extract, Set, ClearNormalization, Saturation, Bit-CountingCompact 16-Bit InstructionsAdditional Instructions to Support Complex MultipliesARM Cortex-A8 CoreARMv7 ArchitectureTrustZone®Thumb®-2MMU EnhancementsIn-Order, Dual-Issue, Superscalar Microprocessor CoreNEON Multimedia ArchitectureOver 2x Performance of ARMv6 SIMDSupports Both Integer and Floating-Point SIMDJazelle® RCT Execution Environment ArchitectureDynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return StackEmbedded Trace Macrocell (ETM) Support for Noninvasive DebugARM Cortex-A8 Memory Architecture:16-KB Instruction Cache (4-Way Set-Associative)16-KB Data Cache (4-Way Set-Associative)256-KB L2 Cache112KB of ROM64KB of Shared SRAMEndianess:ARM Instructions – Little EndianARM Data – ConfigurableDSP Instruction and Data - Little EndianExternal Memory Interfaces:SDRAM Controller (SDRC)16- and 32-Bit Memory Controller with 1GB of Total Address SpaceInterfaces to Low-Power Double Data Rate (LPDDR) SDRAMSDRAM Memory Scheduler (SMS) and Rotation EngineGeneral Purpose Memory Controller (GPMC)16-Bit-Wide Multiplexed Address and Data BusUp to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select PinGlueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAMFlexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)Camera Image Signal Processor (ISP)CCD and CMOS Imager InterfaceMemory Data InputBT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 InterfaceGlueless Interface to Common Video DecodersResize EngineResize Images From 1/4x to 4xSeparate Horizontal and Vertical ControlDisplay SubsystemParallel Digital OutputUp to 24-Bit RGBHD Maximum ResolutionSupports Up to 2 LCD PanelsSupport for Remote Frame Buffer Interface (RFBI) LCD Panels2 10-Bit Digital-to-Analog Converters (DACs) Supporting:Composite NTSC and PAL VideoLuma and Chroma Separate Video (S-Video)Rotation 90-, 180-, and 270-DegreesResize Images From 1/4x to 8xColor Space Converter8-Bit Alpha BlendingSerial Communication5 Multichannel Buffered Serial Ports (McBSPs)512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)5-KB Transmit and Receive Buffer (McBSP2)SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix OperationsDirect Interface to I2S and PCM Device and TDM Buses128-Channel Transmit and Receive ModeFour Master or Slave Multichannel Serial Port Interface (McSPI) PortsHigh-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)High-, Full-, and Low-Speed Multiport USB Host Subsystem12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial InterfaceSupports Transceiverless Link Logic (TLL)One HDQ™/1-Wire® InterfaceThree UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) ControllersRemovable Media Interfaces:Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)Comprehensive Power, Reset, and Clock ManagementSmartReflex™ TechnologyDynamic Voltage and Frequency Scaling (DVFS)Test InterfacesIEEE 1149.1 (JTAG) Boundary-Scan CompatibleETM InterfaceSerial Data Transport Interface (SDTI)12 32-Bit General-Purpose Timers2 32-Bit Watchdog Timers1 32-Bit 32-kHz Sync TimerUp to 188 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)65-nm CMOS TechnologiesPackage-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)Discrete Memory Interface (Not Available in CBC Package)Packages:515-pin s-PBGA Package (CBB Suffix),.5-mm Ball Pitch (Top), .4-mm Ball Pitch (Bottom)515-pin s-PBGA Package (CBC Suffix),.65-mm Ball Pitch (Top), .5-mm Ball Pitch (Bottom)423-pin s-PBGA Package (CUS Suffix),.65-mm Ball Pitch1.8-V I/O and 3.0-V (MMC1 Only),0.985-V to 1.35-V Adaptive Processor Core Voltage0.985-V to 1.35-V Adaptive Core Logic VoltageNote: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.

Description

OMAP3530 and OMAP3525 devices are based on the enhanced OMAP 3 architecture. The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: The device supports high-level operating systems (HLOSs), such as: This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device: The device also offers: OMAP3530 and OMAP3525 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences). This data manual presents the electrical and mechanical specifications for the OMAP3530 and OMAP3525 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP3530 and OMAP3525 applications processors unless otherwise indicated. This data manual consists of the following sections: OMAP3530 and OMAP3525 devices are based on the enhanced OMAP 3 architecture. The OMAP 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following: The device supports high-level operating systems (HLOSs), such as: This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products. The following subsystems are part of the device: The device also offers: OMAP3530 and OMAP3525 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package. (See Table 1-1 for package differences). This data manual presents the electrical and mechanical specifications for the OMAP3530 and OMAP3525 applications processors. The information in this data manual applies to both the commercial and extended temperature versions of the OMAP3530 and OMAP3525 applications processors unless otherwise indicated. This data manual consists of the following sections: