OMAPL137-HT Series

High temperature low power C674x floating-point DSP + Arm processor - up to 456 MHz

Catalog

High temperature low power C674x floating-point DSP + Arm processor - up to 456 MHz

Part	Additional Interfaces	Core Processor	Display & Interface Controllers	Voltage - I/O	Mounting Type	Speed	Co-Processors/DSP	Supplier Device Package	Number of Cores/Bus Width	Package / Case	Ethernet	Ethernet [Max]	Ethernet [Min]	USB	Operating Temperature [Min]	Operating Temperature [Max]	Operating Temperature [custom]
Texas Instruments OMAPL137BPTPH	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	300 MHz	C674x CP15 Signal Processing System Control	176-HLQFP (24x24)	1 Core 32 Bit	176-LQFP Exposed Pad	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)	-55 °C	175 ░C
Texas Instruments OMAPL137BZKBT3	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	375 MHz	C674x CP15 Signal Processing System Control	256-BGA (17x17)	1 Core 32 Bit	256-BGA	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)	-40 °C	125 ¯C
Texas Instruments OMAPL137DZKBT3	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	375 MHz	C674x CP15 Signal Processing System Control	256-BGA (17x17)	1 Core 32 Bit	256-BGA	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)	-40 °C	125 ¯C
Texas Instruments OMAPL137BZKBD4	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	456 MHz	C674x CP15 Signal Processing System Control	256-BGA (17x17)	1 Core 32 Bit	256-BGA	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)	-40 °C	90 °C
Texas Instruments OMAPL137BZKBA3	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	375 MHz	C674x CP15 Signal Processing System Control	256-BGA (17x17)	1 Core 32 Bit	256-BGA	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)			-40 °C 105 °C
Texas Instruments OMAPL137AZKB3	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	300 MHz	C674x CP15 Signal Processing System Control	256-BGA (17x17)	1 Core 32 Bit	256-BGA	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)	0 °C	90 °C
Texas Instruments OMAPL137DZKB3	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	375 MHz	C674x CP15 Signal Processing System Control	256-BGA (17x17)	1 Core 32 Bit	256-BGA	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)	0 °C	90 °C
Texas Instruments OMAPL137CZKB3	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	375 MHz	C674x CP15 Signal Processing System Control	256-BGA (17x17)	1 Core 32 Bit	256-BGA	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)	0 °C	90 °C
Texas Instruments OMAPL137CZKB4	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	456 MHz	C674x CP15 Signal Processing System Control	256-BGA (17x17)	1 Core 32 Bit	256-BGA	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)	0 °C	90 °C
Texas Instruments OMAPL137BZKB3	HPI I2C McASP MMC/SD SPI UART	ARM926EJ-S	LCD	1.8 V 3.3 V	Surface Mount	375 MHz	C674x CP15 Signal Processing System Control	256-BGA (17x17)	1 Core 32 Bit	256-BGA	1	100 Mbps	10 Mbps	USB 1.1 + PHY (1) USB 2.0 + PHY (1)	0 °C	90 °C

Catalog

High temperature low power C674x floating-point DSP + Arm processor - up to 456 MHz

Key Features

• HighlightsDual Core SoC300-MHz ARM926EJ-S RISC MPU300-MHz C674x™ VLIW DSPTMS320C674x Fixed/Floating-Point VLIW DSP CoreEnhanced Direct-Memory-Access Controller 3 (EDMA3)128K-Byte RAM Shared MemoryTwo External Memory InterfacesTwo External Memory Interfaces ModulesLCD ControllerTwo Serial Peripheral Interfaces (SPI)Multimedia Card (MMC)/Secure Digital (SD)Two Master/Slave Inter-Integrated CircuitOne Host-Port Interface (HPI)USB 1.1 OHCI (Host) With Integrated PHY (USB1)ApplicationsIndustrial DiagnosticsTest and measurementMilitary Sonar/RadarMedical measurementProfessional AudioDown Hole IndustrySoftware SupportTI DSP/BIOSChip Support Library and DSP LibraryARM926EJ-S Core32-Bit and 16-Bit (Thumb®) InstructionsDSP Instruction ExtensionsSingle Cycle MACARM Jazelle TechnologyEmbeddedICE-RT for Real-Time DebugARM9 Memory ArchitectureC674x Instruction Set FeaturesSuperset of the C67x+ and C64x+ ISAsUp to 3648/2736 C674x MIPS/MFLOPSByte-Addressable (8-/16-/32-/64-Bit Data)8-Bit Overflow ProtectionBit-Field Extract, Set, ClearNormalization, Saturation, Bit-CountingCompact 16-Bit InstructionsC674x Two Level Cache Memory Architecture32K-Byte L1P Program RAM/Cache32K-Byte L1D Data RAM/Cache256K-Byte L2 Unified Mapped RAM/CacheFlexible RAM/Cache Partition (L1 and L2)1024KB L2 ROMEnhanced Direct-Memory-Access Controller 3 (EDMA3):2 Transfer Controllers32 Independent DMA Channels8 Quick DMA ChannelsProgrammable Transfer Burst SizeTMS320C674x™ Fixed/Floating-Point VLIW DSP CoreLoad-Store Architecture With Non-Aligned Support64 General-Purpose Registers (32 Bit)Six ALU (32-/40-Bit) Functional UnitsSupports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) andDP (IEEE Double Precision/64-Bit) Floating PointSupports up to Four SP Additions Per Clock, Four DP AdditionsEvery 2 ClocksSupports up to Two Floating Point (SP or DP) Approximate Reciprocalor Square Root Operations Per CycleTwo Multiply Functional UnitsMixed-Precision IEEE Floating Point Multiply Supported up to:2 SP × SP > SP Per Clock2 SP × SP > DP Every Two Clocks2 SP × DP > DP Every Three Clocks2 DP × DP > DP Every Four ClocksFixed Point Multiply Supports Two 32 × 32-Bit Multiplies,Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multipliesper Clock Cycle, and Complex MultiplesInstruction Packing Reduces Code SizeAll Instructions ConditionalHardware Support for Modulo Loop OperationProtected Mode OperationExceptions Support for Error Detection and Program Redirection128K-Byte RAM Shared Memory3.3V LVCMOS IOs (except for USB interfaces)Two External Memory Interfaces:EMIFANOR (8-/16-Bit-Wide Data)NAND (8-/16-Bit-Wide Data)16-Bit SDRAM With 128MB Address SpaceEMIFB32-Bit or 16-Bit SDRAM With 256MB Address SpaceThree Configurable 16550 type UART Modules:UART0 With Modem Control SignalsAutoflow control signals (CTS, RTS) on UART0 only16-byte FIFO16x or 13x Oversampling OptionLCD ControllerTwo Serial Peripheral Interfaces (SPI) Each With One Chip-SelectMultimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)Two Master/Slave Inter-Integrated Circuit (I2CBus™)One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High BandwidthProgrammable Real-Time Unit Subsystem (PRUSS)Two Independent Programmable Realtime Unit (PRU) Cores32-Bit Load/Store RISC architecture4K Byte instruction RAM per core512 Bytes data RAM per corePRU Subsystem (PRUSS) can be disabled via software to save powerStandard Power Management MechanismClock GatingEntire Subsystem Under a Single PSC Clock Gating DomainDedicated Interrupt ControllerDedicated Switched Central ResourceUSB 1.1 OHCI (Host) With Integrated PHY (USB1)USB 2.0 OTG Port With Integrated PHY (USB0):USB 2.0 High-/Full-Speed ClientUSB 2.0 High-/Full-/Low-Speed HostEnd Point 0 (Control)End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and TxThree Multichannel Audio Serial Ports:Six Clock Zones and 28 Serial Data PinsSupports TDM, I2S, and Similar FormatsDIT-Capable (McASP2)FIFO buffers for Transmit and Receive10/100 Mb/s Ethernet MAC (EMAC):IEEE 802.3 Compliant (3.3-V I/O Only)RMII Media Independent InterfaceManagement Data I/O (MDIO) ModuleReal-Time Clock With 32 KHz Oscillator and Separate Power RailCrystal oscillators not validated beyond 125°C. Recommend use of external oscillator.One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)One 64-Bit General-Purpose Timer/Watchdog Timer (Configurable as Two 32-bitGeneral-Purpose Timers)Three Enhanced Pulse Width Modulators (eHRPWM):Dedicated 16-Bit Time-Base Counter With Period And Frequency Control6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric OutputsDead-Band GenerationPWM Chopping by High-Frequency CarrierTrip Zone InputThree 32-Bit Enhanced Capture Modules (eCAP):Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputsSingle Shot Capture of up to Four Event Time-StampsTwo 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)176-pin PowerPADTMPlastic Quad Flat Pack [PTP suffix], 0.5-mm Pin PitchHigh Temperature (175°C) ApplicationTexas Instruments High Temperature Products Use Highly Optimized Silicon Solutions withDesign and Process Enhancements to Maximize Performance over Extended Temperatures.All Devices are Characterized and Qualified for 1000 Hours Continuous Operating Lifeat Maximum Rated TemperatureCommunity ResourcesTI E2E CommunityTI Embedded Processors WikiHighlightsDual Core SoC300-MHz ARM926EJ-S RISC MPU300-MHz C674x™ VLIW DSPTMS320C674x Fixed/Floating-Point VLIW DSP CoreEnhanced Direct-Memory-Access Controller 3 (EDMA3)128K-Byte RAM Shared MemoryTwo External Memory InterfacesTwo External Memory Interfaces ModulesLCD ControllerTwo Serial Peripheral Interfaces (SPI)Multimedia Card (MMC)/Secure Digital (SD)Two Master/Slave Inter-Integrated CircuitOne Host-Port Interface (HPI)USB 1.1 OHCI (Host) With Integrated PHY (USB1)ApplicationsIndustrial DiagnosticsTest and measurementMilitary Sonar/RadarMedical measurementProfessional AudioDown Hole IndustrySoftware SupportTI DSP/BIOSChip Support Library and DSP LibraryARM926EJ-S Core32-Bit and 16-Bit (Thumb®) InstructionsDSP Instruction ExtensionsSingle Cycle MACARM Jazelle TechnologyEmbeddedICE-RT for Real-Time DebugARM9 Memory ArchitectureC674x Instruction Set FeaturesSuperset of the C67x+ and C64x+ ISAsUp to 3648/2736 C674x MIPS/MFLOPSByte-Addressable (8-/16-/32-/64-Bit Data)8-Bit Overflow ProtectionBit-Field Extract, Set, ClearNormalization, Saturation, Bit-CountingCompact 16-Bit InstructionsC674x Two Level Cache Memory Architecture32K-Byte L1P Program RAM/Cache32K-Byte L1D Data RAM/Cache256K-Byte L2 Unified Mapped RAM/CacheFlexible RAM/Cache Partition (L1 and L2)1024KB L2 ROMEnhanced Direct-Memory-Access Controller 3 (EDMA3):2 Transfer Controllers32 Independent DMA Channels8 Quick DMA ChannelsProgrammable Transfer Burst SizeTMS320C674x™ Fixed/Floating-Point VLIW DSP CoreLoad-Store Architecture With Non-Aligned Support64 General-Purpose Registers (32 Bit)Six ALU (32-/40-Bit) Functional UnitsSupports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) andDP (IEEE Double Precision/64-Bit) Floating PointSupports up to Four SP Additions Per Clock, Four DP AdditionsEvery 2 ClocksSupports up to Two Floating Point (SP or DP) Approximate Reciprocalor Square Root Operations Per CycleTwo Multiply Functional UnitsMixed-Precision IEEE Floating Point Multiply Supported up to:2 SP × SP > SP Per Clock2 SP × SP > DP Every Two Clocks2 SP × DP > DP Every Three Clocks2 DP × DP > DP Every Four ClocksFixed Point Multiply Supports Two 32 × 32-Bit Multiplies,Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multipliesper Clock Cycle, and Complex MultiplesInstruction Packing Reduces Code SizeAll Instructions ConditionalHardware Support for Modulo Loop OperationProtected Mode OperationExceptions Support for Error Detection and Program Redirection128K-Byte RAM Shared Memory3.3V LVCMOS IOs (except for USB interfaces)Two External Memory Interfaces:EMIFANOR (8-/16-Bit-Wide Data)NAND (8-/16-Bit-Wide Data)16-Bit SDRAM With 128MB Address SpaceEMIFB32-Bit or 16-Bit SDRAM With 256MB Address SpaceThree Configurable 16550 type UART Modules:UART0 With Modem Control SignalsAutoflow control signals (CTS, RTS) on UART0 only16-byte FIFO16x or 13x Oversampling OptionLCD ControllerTwo Serial Peripheral Interfaces (SPI) Each With One Chip-SelectMultimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)Two Master/Slave Inter-Integrated Circuit (I2CBus™)One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High BandwidthProgrammable Real-Time Unit Subsystem (PRUSS)Two Independent Programmable Realtime Unit (PRU) Cores32-Bit Load/Store RISC architecture4K Byte instruction RAM per core512 Bytes data RAM per corePRU Subsystem (PRUSS) can be disabled via software to save powerStandard Power Management MechanismClock GatingEntire Subsystem Under a Single PSC Clock Gating DomainDedicated Interrupt ControllerDedicated Switched Central ResourceUSB 1.1 OHCI (Host) With Integrated PHY (USB1)USB 2.0 OTG Port With Integrated PHY (USB0):USB 2.0 High-/Full-Speed ClientUSB 2.0 High-/Full-/Low-Speed HostEnd Point 0 (Control)End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and TxThree Multichannel Audio Serial Ports:Six Clock Zones and 28 Serial Data PinsSupports TDM, I2S, and Similar FormatsDIT-Capable (McASP2)FIFO buffers for Transmit and Receive10/100 Mb/s Ethernet MAC (EMAC):IEEE 802.3 Compliant (3.3-V I/O Only)RMII Media Independent InterfaceManagement Data I/O (MDIO) ModuleReal-Time Clock With 32 KHz Oscillator and Separate Power RailCrystal oscillators not validated beyond 125°C. Recommend use of external oscillator.One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)One 64-Bit General-Purpose Timer/Watchdog Timer (Configurable as Two 32-bitGeneral-Purpose Timers)Three Enhanced Pulse Width Modulators (eHRPWM):Dedicated 16-Bit Time-Base Counter With Period And Frequency Control6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric OutputsDead-Band GenerationPWM Chopping by High-Frequency CarrierTrip Zone InputThree 32-Bit Enhanced Capture Modules (eCAP):Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputsSingle Shot Capture of up to Four Event Time-StampsTwo 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)176-pin PowerPADTMPlastic Quad Flat Pack [PTP suffix], 0.5-mm Pin PitchHigh Temperature (175°C) ApplicationTexas Instruments High Temperature Products Use Highly Optimized Silicon Solutions withDesign and Process Enhancements to Maximize Performance over Extended Temperatures.All Devices are Characterized and Qualified for 1000 Hours Continuous Operating Lifeat Maximum Rated TemperatureCommunity ResourcesTI E2E CommunityTI Embedded Processors Wiki

Description

The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs. The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and data and program Memory Management Units (MMUs) with table look-aside buffers. The ARM core has separate 16-KB instruction and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM. The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance. The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with bothRTSandCTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution. The OMAP-L137 device is a low-power applications processor based on an ARM926EJ-S and a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000 platform of DSPs. The OMAP-L137 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution. The dual-core architecture of the OMAP-L137 device provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core. The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM core has a coprocessor 15 (CP15), protection module, and data and program Memory Management Units (MMUs) with table look-aside buffers. The ARM core has separate 16-KB instruction and 16KB of data caches. Both memory blocks are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM. The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB of RAM shared memory is available for use by other hosts without affecting DSP performance. The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/12/4 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with bothRTSandCTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration. The HPI, I2C, SPI, USB1.1, and USB2.0 ports allow the OMAP-L137 device to easily control peripheral devices and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The OMAP-L137 device has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.