SN74LVC2G2412-ch, 1.65-V to 5.5-V buffers with 3-state outputs | Integrated Circuits (ICs) | 10 | Active | This dual buffer and line driver is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G241 device is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The SN74LVC2G241 device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OEis low and 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OEis high and 2OE is low, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual buffer and line driver is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G241 device is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The SN74LVC2G241 device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OEis low and 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OEis high and 2OE is low, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G32-Q1Automotive, 2-ch, 2-input 1.65-V to 5.5-V 32-mA drive strength OR gate | Logic | 10 | Active | This dual two-input positive-OR gate is designed for 1.65-V to 5.5-V collector supply voltage operation.
The SN74LVC2G32-Q1 performs the Boolean function Y = A + B or Y =A\ • B\in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using the off-state current. The off-state current circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual two-input positive-OR gate is designed for 1.65-V to 5.5-V collector supply voltage operation.
The SN74LVC2G32-Q1 performs the Boolean function Y = A + B or Y =A\ • B\in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using the off-state current. The off-state current circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
| Buffers, Drivers, Receivers, Transceivers | 11 | Active | The SN74LVC2G34 is a dual buffer gate designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC2G34 performs the Boolean function Y = A in positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVC2G34 is a dual buffer gate designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC2G34 performs the Boolean function Y = A in positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G382-ch, 2-input, 1.65-V to 5.5-V NAND gates with open-drain outputs | Gates and Inverters | 6 | Active | The SN74LVC2G38 is designed for 1.65-V to 5.5-V VCCoperation.
This device is a dual two-input NAND buffer gate with open-drain outputs. It performs the Boolean function Y =A • Bor Y =A+Bin positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVC2G38 is designed for 1.65-V to 5.5-V VCCoperation.
This device is a dual two-input NAND buffer gate with open-drain outputs. It performs the Boolean function Y =A • Bor Y =A+Bin positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G535-V, 2:1 (SPDT), 1-channel general-purpose analog switch (available in the NanoFree™ package) | Integrated Circuits (ICs) | 6 | Active | This single 2:1 analog multiplexer/demultiplexer is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G53 device can handle both analog and digital signals. This device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.
This single 2:1 analog multiplexer/demultiplexer is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G53 device can handle both analog and digital signals. This device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. |
SN74LVC2G665-V, 1:1 (SPST), 2-channel general-purpose analog switch with low on-state resistance | Analog Switches, Multiplexers, Demultiplexers | 9 | Active | This dual bilateral analog switch is designed for1.65-V to 5.5-V VCCoperation.
The SN74LVC2G66 device can handle both analog and digital signals. The SN74LVC2G66 device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.
This dual bilateral analog switch is designed for1.65-V to 5.5-V VCCoperation.
The SN74LVC2G66 device can handle both analog and digital signals. The SN74LVC2G66 device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. |
SN74LVC2G74Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset | Logic | 9 | Active | This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCCoperation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCCoperation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G74-Q1Automotive Catalog Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset | Integrated Circuits (ICs) | 1 | Active | This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G79Dual Positive-Edge-Triggered D-Type Flip-Flop | Integrated Circuits (ICs) | 3 | Active | This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G80Dual Positive-Edge-Triggered D-Type Flip-Flop | Flip Flops | 5 | Active | This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.
When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
