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SN74LVC2G80

SN74LVC2G80 Series

Dual Positive-Edge-Triggered D-Type Flip-Flop

Manufacturer: Texas Instruments

Catalog

Dual Positive-Edge-Triggered D-Type Flip-Flop

Key Features

Available in the Texas InstrumentsNanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.2 ns at 3.3 VLow Power Consumption, 10-μA Max ICCTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffFeature Supports Live Insertion, Partial-Power-Down and Back Drive ProtectionMode OperationLatch-Up Performance Exceeds 100 mAPer JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Available in the Texas InstrumentsNanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.2 ns at 3.3 VLow Power Consumption, 10-μA Max ICCTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffFeature Supports Live Insertion, Partial-Power-Down and Back Drive ProtectionMode OperationLatch-Up Performance Exceeds 100 mAPer JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

AI
This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This dual positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. When data at the data (D) input meets the setup time requirement, the data is transferred to theQoutput on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.