SN74LVC2G100Two-channel 1.1V-to-3.6V configurable gate with flip-flop and Schmitt-trigger inputs | Integrated Circuits (ICs) | 1 | Active | The SN74LVC2G100 is a dual, sequential, configurable multiple function device with Schmitt Trigger inputs. Sixteen patterns of a 4-bit input determines the output state. The output state serves as the input to a D-Flip Flop, which is transferred to the Q output on the positive going CLK edge. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and non-inverter.
The SN74LVC2G100 is a dual, sequential, configurable multiple function device with Schmitt Trigger inputs. Sixteen patterns of a 4-bit input determines the output state. The output state serves as the input to a D-Flip Flop, which is transferred to the Q output on the positive going CLK edge. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and non-inverter. |
SN74LVC2G101Two-channel 1.1V-to-3.6V configurable gate for clock input with Schmitt-trigger inputs | Integrated Circuits (ICs) | 1 | Active | The SN74LVC2G101 contains two independent D-type flip-flops. Each channel has data (D), clear (CLR), and clock (CLKA, CLKB, CLKC, CLKD) inputs and a non-inverted output (Q). The clock inputs can be configured for use in a wide variety of applications, allowing for configuration as 2-input AND, OR, NAND, NOR, XOR, XNOR, as well as 1-input inverted or non-inverted operation. All inputs include Schmitt-trigger architecture.
The SN74LVC2G101 contains two independent D-type flip-flops. Each channel has data (D), clear (CLR), and clock (CLKA, CLKB, CLKC, CLKD) inputs and a non-inverted output (Q). The clock inputs can be configured for use in a wide variety of applications, allowing for configuration as 2-input AND, OR, NAND, NOR, XOR, XNOR, as well as 1-input inverted or non-inverted operation. All inputs include Schmitt-trigger architecture. |
SN74LVC2G1252-ch, 1.65-V to 5.5-V buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 11 | Active | The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCCoperation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCCoperation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G1262-ch, 1.65-V to 5.5-V buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 8 | Active | These bus transceivers are designed for 1.65-V to 3.6-V VCCoperation. The SN74LVC2G126 device is a dual line driver with 3-state output. The output is disabled when the output-enable input is low.
These bus transceivers are designed for 1.65-V to 3.6-V VCCoperation. The SN74LVC2G126 device is a dual line driver with 3-state output. The output is disabled when the output-enable input is low. |
SN74LVC2G126-EPEnhanced product 2-ch, 1.65-V to 5.5-V buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 1 | Active | This dual bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G1322-ch, 2-input, 1.65-V to 5.5-V NAND gates with Schmitt-Trigger inputs | Gates and Inverters | 8 | Active | This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G132 contains two inverters and performs the Boolean function Y =A ⋅ Bor Y =A+Bin positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G132 contains two inverters and performs the Boolean function Y =A ⋅ Bor Y =A+Bin positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G142-ch, 1.65-V to 5.5-V inverters with Schmitt-Trigger inputs | Gates and Inverters | 13 | Active | This dual Schmitt-trigger inverter is designed for1.65-V to 5.5-V VCCoperation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The SN74LVC2G14 device contains two inverters and performs the Boolean function Y =A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual Schmitt-trigger inverter is designed for1.65-V to 5.5-V VCCoperation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The SN74LVC2G14 device contains two inverters and performs the Boolean function Y =A. The device functions as two independent inverters, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G157Single 2-Line to 1-Line Data Selector/Multiplexer | Signal Switches, Multiplexers, Decoders | 11 | Active | This single 2-line to 1-line data selector multiplexer is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G157 device features a common strobe (G) input. When the strobe is high, Y is low andYis high. When the strobe is low, a single bit is selected from one of two sources and is routed to the outputs. The device provides true and complementary data.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single 2-line to 1-line data selector multiplexer is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G157 device features a common strobe (G) input. When the strobe is high, Y is low andYis high. When the strobe is low, a single bit is selected from one of two sources and is routed to the outputs. The device provides true and complementary data.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G17-Q1Enhanced product 2-ch, 1.65-V to 5.5-V buffers with Schmitt-Trigger inputs | Logic | 20 | Active | This dual Schmitt-Trigger buffer is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G17 device contains two buffers and performs the Boolean function Y = A. The device functions as two independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual Schmitt-Trigger buffer is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G17 device contains two buffers and performs the Boolean function Y = A. The device functions as two independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC2G2402-ch, 1.65-V to 5.5-V inverters with 3-state outputs | Integrated Circuits (ICs) | 6 | Active | This dual buffer driver is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A input to the Y output. WhenOEis high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This dual buffer driver is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A input to the Y output. WhenOEis high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
