SN74LVC2G862-ch, 2-input, 1.65-V to 5.5-V XOR (exclusive OR) gates | Integrated Circuits (ICs) | 10 | Active | This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G86 performs the Boolean function Y = A ⊕ B or Y =AB + ABin positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.
This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2G86 performs the Boolean function Y = A ⊕ B or Y =AB + ABin positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. |
| Integrated Circuits (ICs) | 6 | Active | This dual inverter is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2GU04 device contains two inverters with unbuffered outputs and performs the Boolean function Y =A.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This dual inverter is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC2GU04 device contains two inverters with unbuffered outputs and performs the Boolean function Y =A.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. |
SN74LVC2T45-EPEnhanced Product Dual-Bit Dual Supply Transceiver w/ Configurable Voltage Transl., 3-State Outputs | Integrated Circuits (ICs) | 11 | Active | This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCAaccepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCBaccepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICCand ICCZ.
The SN74LVC2T45 is designed so that the DIR input circuit is supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCCisolation feature ensures that if either VCCinput is at GND, both ports are in the high-impedance state.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCAaccepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCBaccepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICCand ICCZ.
The SN74LVC2T45 is designed so that the DIR input circuit is supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCCisolation feature ensures that if either VCCinput is at GND, both ports are in the high-impedance state.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. |
SN74LVC32A-EPEnhanced product, 4-ch, 2-input 2-V to 3.6-V 24-mA drive strength OR gate | Gates and Inverters | 18 | Active | The SN74LVC32A quadruple 2-input positive-OR gate is designed for 2.7-V to 3.6-V VCCoperation.
The device performs the Boolean function Y = A + B or Y =A\ • B\in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
The SN74LVC32A quadruple 2-input positive-OR gate is designed for 2.7-V to 3.6-V VCCoperation.
The device performs the Boolean function Y = A + B or Y =A\ • B\in positive logic.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. |
SN74LVC373AOctal Transparent D-Type Latch With 3-State Outputs | Logic | 15 | Active | The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation.
The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation. |
SN74LVC374A-EPEnhanced Product Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs | Flip Flops | 14 | Active | The SN74LVC374A-EP octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVC374A-EP octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
SN74LVC374A-Q1Automotive Catalog Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs | Flip Flops | 1 | Active | The SN74LVC374A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, (OE) should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVC374A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, (OE) should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Logic | 8 | Active | This triple inverter is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC3G04 device performs the Boolean function Y =A.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This triple inverter is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC3G04 device performs the Boolean function Y =A.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC3G063-ch, 1.65-V to 5.5-V inverters with open-drain outputs | Gates and Inverters | 7 | Active | This triple inverter buffer/driver is designed for 1.65-V to 5.5-V VCCoperation.
The output of the SN74LVC3G06 is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This triple inverter buffer/driver is designed for 1.65-V to 5.5-V VCCoperation.
The output of the SN74LVC3G06 is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC3G07-Q1Automotive 3-ch, 1.65-V to 5.5-V buffers with open-drain outputs | Integrated Circuits (ICs) | 9 | Active | This triple buffer/driver is designed for 1.65-V to 5.5-V VCCoperation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The output of the SN74LVC3G07 is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This triple buffer/driver is designed for 1.65-V to 5.5-V VCCoperation.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The output of the SN74LVC3G07 is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
