SN74LVC2G74-Q1 Series

Automotive Catalog Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Catalog

Automotive Catalog Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Part	Operating Temperature [Min]	Operating Temperature [Max]	Current - Output High, Low	Mounting Type	Input Capacitance	Number of Bits per Element	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Elements	Clock Frequency	Max Propagation Delay @ V, Max CL	Qualification	Type	Grade	Trigger Type	Function	Current - Quiescent (Iq)	Output Type	Package / Case [y]	Package / Case	Package / Case [y]
Texas Instruments CLVC2G74QDCURG4Q1	-40 °C	125 °C	24 mA	Surface Mount	5 pF	1	5.5 V	1.65 V	1	140 MHz	5.1 ns	AEC-Q100	D-Type	Automotive	Positive Edge	Reset Set(Preset)	10 µA	Complementary	2.3 mm	8-VFSOP	0.091 in

Catalog

Automotive Catalog Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

Key Features

• Qualified for Automotive ApplicationsSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 6.9 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Qualified for Automotive ApplicationsSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 6.9 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2 V at VCC= 3.3 V, TA= 25°CIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.