SN74LVC165A1.1V to 3.6V parallel-load eight-bit shift registers | Shift Registers | 1 | Active | The SN74LVC165A contains one 8-bit parallel-load shift register. Data is loaded asynchronously using the shift or load (SH/LD) select pin. The device includes a serial (SER) input to allow for daisy chaining, and a standard (QH) and inverted (QH) output.
The SN74LVC165A contains one 8-bit parallel-load shift register. Data is loaded asynchronously using the shift or load (SH/LD) select pin. The device includes a serial (SER) input to allow for daisy chaining, and a standard (QH) and inverted (QH) output. |
SN74LVC165A-Q1Automotive, 1.1V to 3.6V parallel-load eight-bit shift registers | Logic | 1 | Active | The SN74LVC165A-Q1 contains one 8-bit parallel-load shift register. Data is loaded asynchronously using the shift or load (SH/LD) select pin. The device includes a serial (SER) input to allow for daisy chaining, and a standard (QH) and inverted (QH) output.
The SN74LVC165A-Q1 contains one 8-bit parallel-load shift register. Data is loaded asynchronously using the shift or load (SH/LD) select pin. The device includes a serial (SER) input to allow for daisy chaining, and a standard (QH) and inverted (QH) output. |
SN74LVC16646A16-Bit Bus Transceiver And Register With 3-State Outputs | Buffers, Drivers, Receivers, Transceivers | 7 | Active | This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC16646A can be used as two 8-bit transceivers or one 16-bit transceiver. The device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVC16646A.
Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE\ is low. In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
When an output function is disabled, the input function still is enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 16-bit bus transceiver and register is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC16646A can be used as two 8-bit transceivers or one 16-bit transceiver. The device consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the SN74LVC16646A.
Output-enable (OE\) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the high-impedance port can be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE\ is low. In the isolation mode (OE\ high), A data can be stored in one register and/or B data can be stored in the other register.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
When an output function is disabled, the input function still is enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
SN74LVC16T245-EP16-bit dual-supply bus transceiver with configurable level-shifting / voltage translation | Integrated Circuits (ICs) | 8 | Active | This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCAaccepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCBaccepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC16T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICCand ICCZ.
The SN74LVC16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCCisolation feature ensures that if either VCCinput is at GND, then both ports are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCAaccepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCBaccepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
The SN74LVC16T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) input activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICCand ICCZ.
The SN74LVC16T245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The VCCisolation feature ensures that if either VCCinput is at GND, then both ports are in the high-impedance state.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Analog Switches, Multiplexers, Demultiplexers | 2 | Obsolete | |
SN74LVC1G00-EPEnhanced product single 1-input, 1.65-V to 5.5-V NAND gate | Logic | 25 | Active | This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G00 performs the Boolean functionY =A × Bor Y =A+Bin positive logic.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range.
The SN74LVC1G00 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G00 performs the Boolean functionY =A × Bor Y =A+Bin positive logic.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range.
The SN74LVC1G00 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm. |
SN74LVC1G02-EPEnhanced product single 2-input, 1.65-V to 5.5-V NOR gate | Gates and Inverters | 17 | Active | This single 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G02 performs the Boolean function Y =A + Bor Y =A×Bin positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G02 performs the Boolean function Y =A + Bor Y =A×Bin positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
| Integrated Circuits (ICs) | 25 | Active | This single inverter gate is designed for1.65-V to 5.5-V VCCoperation.
The SN74LVC1G04 device performs the Boolean function Y =A.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range.
The SN74LVC1G04 device is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.
This single inverter gate is designed for1.65-V to 5.5-V VCCoperation.
The SN74LVC1G04 device performs the Boolean function Y =A.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range.
The SN74LVC1G04 device is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm. |
SN74LVC1G06-EPEnhanced product single 1.65-V to 5.5-V inverter with open-drain outputs | Integrated Circuits (ICs) | 18 | Active | This single inverter buffer and driver is designed for 1.65-V to 5.5-V VCCoperation.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The output of the SN74LVC1G06 device is open-drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using Ioff.The Ioffcircuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
This single inverter buffer and driver is designed for 1.65-V to 5.5-V VCCoperation.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The output of the SN74LVC1G06 device is open-drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using Ioff.The Ioffcircuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. |
SN74LVC1G07-Q1Enhanced product single 1.65-V to 5.5-V buffer with open-drain outputs | Buffers, Drivers, Receivers, Transceivers | 31 | Active | The SN74LVC1G07-Q1 is a single channel open-drain buffer/driver qualified for automotive applications. This is designed for 1.65-V to 5.5-V VCCoperation.
The output of the SN74LVC1G07-Q1 device is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using Ioff.The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G07-Q1 is a single channel open-drain buffer/driver qualified for automotive applications. This is designed for 1.65-V to 5.5-V VCCoperation.
The output of the SN74LVC1G07-Q1 device is open drain and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 32 mA.
This device is fully specified for partial-power-down applications using Ioff.The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
