SN74LVC14A-EPEnhanced product 6-ch, 2-V to 3.6-V inverters with Schmitt-Trigger inputs | Gates and Inverters | 23 | Active | The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V VCCoperation.
The devices contain six independent inverters and perform the Boolean function Y =A.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V or 5-V system environment.
The SN54LVC14A hex Schmitt-trigger inverter is designed for 2.7-V to 3.6-V VCCoperation, and the SN74LVC14A hex Schmitt-trigger inverter is designed for 1.65-V to 3.6-V VCCoperation.
The devices contain six independent inverters and perform the Boolean function Y =A.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V or 5-V system environment. |
SN74LVC157A-Q1Enhanced Product quadruple 2-line to 1-line data selector / multiplexer | Logic | 21 | Active | The SN74LVC157A-EP quadruple 2-line to 1-line data selector/multiplexer is designed for 2.7-V to 3.6-V VCCoperation.
This device features a common strobe (G)\ input. When G\ is high, all outputs are low. When G\ is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The device provides true data.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
The SN74LVC157A-EP quadruple 2-line to 1-line data selector/multiplexer is designed for 2.7-V to 3.6-V VCCoperation.
This device features a common strobe (G)\ input. When G\ is high, all outputs are low. When G\ is low, a 4-bit word is selected from one of two sources and is routed to the four outputs. The device provides true data.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. |
| Logic | 1 | Obsolete | |
| Specialty Logic | 5 | Active | The SN74LVC161284 is designed for 3-V to 3.6-V VCCoperation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LVC161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-kintegrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCCCABLE. If VCCCABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCCis designed for 3-V to 3.6-V operation. VCCCABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCCCABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.
The SN74LVC161284 is characterized for operation from 0°C to 70°C.
The SN74LVC161284 is designed for 3-V to 3.6-V VCCoperation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LVC161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level 1 type) and IEEE Std 1284-II (level 2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-kintegrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCCCABLE. If VCCCABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCCis designed for 3-V to 3.6-V operation. VCCCABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCCCABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.
The SN74LVC161284 is characterized for operation from 0°C to 70°C. |
| Buffers, Drivers, Receivers, Transceivers | 11 | Active | This 16-bit buffer or driver is designed for 1.65-V to 3.6-V VCCoperation. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
This 16-bit buffer or driver is designed for 1.65-V to 3.6-V VCCoperation. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. |
| Logic | 9 | Active | This 16-bit buffer/driver is designed for 1.65-V to3.6-V VCCoperation.
The SN74LVC16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SN74LVC16244A device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The device provides true outputs and symmetrical active-low output-enable (OE) inputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 16-bit buffer/driver is designed for 1.65-V to3.6-V VCCoperation.
The SN74LVC16244A device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SN74LVC16244A device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. The device provides true outputs and symmetrical active-low output-enable (OE) inputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V and 5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Integrated Circuits (ICs) | 1 | Active | This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC16244A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC16244A is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
| Buffers, Drivers, Receivers, Transceivers | 10 | Active | This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC16245A device is designed for asynchronous communication between data buses.
This device can be used as two 8-bit transceivers or one 16-bit transceiver.
This 16-bit (dual-octal) noninverting bus transceiver is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC16245A device is designed for asynchronous communication between data buses.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. |
SN74LVC16373A-EPEnhanced Product 16-Bit Transparent D-Type Latch With 3-State Outputs | Logic | 14 | Active | This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCCoperation.
The SN74LVC16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
OEdoes not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC16374A16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs | Logic | 8 | Active | This 16-bit edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.
The SN74LVC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16374 is characterized for operation from -40°C to 85°C.
This 16-bit edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCCoperation.
The SN74LVC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE\ does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74LVC16374 is characterized for operation from -40°C to 85°C. |
