SN74LVC1G08-EPEnhanced product, 1-ch, 2-input 1.65-V to 5.5-V 32-mA drive strength AND gate | Logic | 25 | Active | This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G08-Q1 device performs the Boolean function or in positive logic.
This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range.
The SN74LVC1G08 is available in a variety of packages, including the small DRY package with a body size of 1.45 mm × 1.00 mm.
This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G08-Q1 device performs the Boolean function or in positive logic.
This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range.
The SN74LVC1G08 is available in a variety of packages, including the small DRY package with a body size of 1.45 mm × 1.00 mm. |
| Integrated Circuits (ICs) | 6 | Active | This device is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic.
By tying one input to GND or VCC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to VCC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to VCC(Y = A + C).
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This device is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic.
By tying one input to GND or VCC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to VCC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to VCC(Y = A + C).
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
| Integrated Circuits (ICs) | 4 | Active | The SN74LVC1G10 performs the Boolean function Y =A • B • Cor Y =A+B+Cin positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G10 performs the Boolean function Y =A • B • Cor Y =A+B+Cin positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC1G11-EPEnhanced product, 1-ch, 3-input 1.65-V to 5.5-V 32-mA drive strength AND gate | Integrated Circuits (ICs) | 9 | Active | The SN74LVC1G11 performs the Boolean function Y = A • B • C or Y =A\ + B\ + C\in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G11 performs the Boolean function Y = A • B • C or Y =A\ + B\ + C\in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC1G123Single retriggerable monostable multivibrator with Schmitt-trigger inputs | Multivibrators | 8 | Active | The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65V to 5.5V VCC operation.
This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear ( CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs.
The SN74LVC1G123 device is a single retriggerable monostable multivibrator designed for 1.65V to 5.5V VCC operation.
This monostable multivibrator features output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear ( CLR) input goes high.
The output pulse duration is programmed by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. The A and B inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. |
SN74LVC1G125Single 1.65-V to 5.5-V buffer with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 16 | Active | This bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range.
The SN74LVC1G125 device is available in a variety of packages including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.
This bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range.
The SN74LVC1G125 device is available in a variety of packages including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm. |
SN74LVC1G125-EPEnhanced product single 1.65-V to 5.5-V buffer with 3-state outputs | Integrated Circuits (ICs) | 4 | Active | This bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. |
SN74LVC1G126Single 1.65-V to 5.5-V buffer with 3-state outputs | Logic | 18 | Active | This single buffer is designed for 1.65-V to 3.6-V VCCoperation. The LVC1G126 device is a single line driver with 3-state output. The output is disabled when the output-enable input is low.
This single buffer is designed for 1.65-V to 3.6-V VCCoperation. The LVC1G126 device is a single line driver with 3-state output. The output is disabled when the output-enable input is low. |
SN74LVC1G126-EPEnhanced product single 1.65-V to 5.5-V buffer with 3-state outputs | Logic | 2 | Active | This single bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
This single bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G126 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. |
SN74LVC1G126-Q1Automotive single 1.65-V to 5.5-V buffer with 3-state outputs | Integrated Circuits (ICs) | 3 | Active | The SN74LVC1G126-Q1 device is a single line driver with 3-state output. The output is disabled when the output-enable input is low.
The SN74LVC1G126-Q1 device is a single line driver with 3-state output. The output is disabled when the output-enable input is low. |
