Texas Instruments

Automotive, three-channel three-input 1.1V-to-3.6V AND gates with 24mA drive strength

This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation. The SN74LVC125A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment. This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation. The SN74LVC125A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.

This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation. This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation.

The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment. The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.

The SN74LVC132A device is a quadruple positive-NAND gate with Schmitt-trigger inputs for added noise immunity and support for slow input signal transitions. Each gate performs the Boolean function Y = A × B or Y = A + B in positive logic. The SN74LVC132A device is a quadruple positive-NAND gate with Schmitt-trigger inputs for added noise immunity and support for slow input signal transitions. Each gate performs the Boolean function Y = A × B or Y = A + B in positive logic.

The SN74LVC132A-Q1 device is a quadruple positive-NAND gate with Schmitt-trigger inputs for added noise immunity and support for slow input signal transitions. Each gate performs the Boolean function Y = A × B or Y = A + B in positive logic. The SN74LVC132A-Q1 device is a quadruple positive-NAND gate with Schmitt-trigger inputs for added noise immunity and support for slow input signal transitions. Each gate performs the Boolean function Y = A × B or Y = A + B in positive logic.

The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation. The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V VCC operation. The device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This dual 2-line to 4-line decoder/demultiplexer is designed for 1.65-V to 3.6-V VCCoperation. The device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable (G)\ input can be used as a data line in demultiplexing applications. This decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This dual 2-line to 4-line decoder/demultiplexer is designed for 1.65-V to 3.6-V VCCoperation. The device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable (G)\ input can be used as a data line in demultiplexing applications. This decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.

This dual 2-line to 4-line decoder/demultiplexer is designed for 1.65-V to 3.6-V VCCoperation. The device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable ((G)) input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment This dual 2-line to 4-line decoder/demultiplexer is designed for 1.65-V to 3.6-V VCCoperation. The device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable ((G)) input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment

The SN74LVC1404 device consists of one inverter with a Schmitt-trigger input and two unbuffered inverters. It is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1404 device consists of one inverter with a Schmitt-trigger input and two unbuffered inverters. It is designed for 1.65-V to 5.5-V VCCoperation.