Texas Instruments

The SN74LV1T04-Q1 contains a single inverter gate with integrated voltage level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output). The SN74LV1T04-Q1 contains a single inverter gate with integrated voltage level translation. Each gate performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The SN74LV1T08 is a single 2-input AND gate with reduced input thresholds to support voltage translation applications. The SN74LV1T08 is a single 2-input AND gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T08-Q1 is a 2-input AND Gate. Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2-V input to 1.8-V output or 1.8-V input to 3.3-V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3-V to 2.5-V output). The SN74LV1T08-Q1 is a 2-input AND Gate. Each gate performs the Boolean function Y = A × B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2-V input to 1.8-V output or 1.8-V input to 3.3-V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3-V to 2.5-V output).

The SN74LV1T125 is a single buffer gate with reduced input thresholds to support voltage translation applications. The SN74LV1T125 is a single buffer gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T125-Q1 is a single buffer gate with 3-state outputs and integrated voltage translation. This buffer performs the Boolean function Y = A in positive logic. The outputs can be placed into a Hi-Z state by applying a High on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output). The SN74LV1T125-Q1 is a single buffer gate with 3-state outputs and integrated voltage translation. This buffer performs the Boolean function Y = A in positive logic. The outputs can be placed into a Hi-Z state by applying a High on the OE pin. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output).

The SN74LV1T126 is a single buffer gate with reduced input thresholds to support voltage translation applications. The SN74LV1T126 is a single buffer gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T32 is a single 2-input OR gate with reduced input thresholds to support voltage translation applications. The SN74LV1T32 is a single 2-input OR gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T32-Q1 is a 2-input OR Gate. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output). The SN74LV1T32-Q1 is a 2-input OR Gate. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

The SN74LV1T34 is a single buffer gate with reduced input thresholds to support voltage translation applications. The SN74LV1T34 is a single buffer gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T34-Q1 contains a single buffer with extended voltage operation to allow for level translation. The buffer performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output). The SN74LV1T34-Q1 contains a single buffer with extended voltage operation to allow for level translation. The buffer performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage (V CC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example 1.2 V input to 1.8 V output or 1.8 V input to 3.3 V output). Additionally, the 5-V tolerant input pins enable down translation (for example 3.3 V to 2.5 V output).