Texas Instruments

The SN74LV1T86 is a single 2-input exclusive OR gate with reduced input thresholds to support voltage translation applications. The SN74LV1T86 is a single 2-input exclusive OR gate with reduced input thresholds to support voltage translation applications.

The SN74LV1T86-Q1 is a 2-input XOR Gate. It performs the Boolean function Y = A ⊕ B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output). The SN74LV1T86-Q1 is a 2-input XOR Gate. It performs the Boolean function Y = A ⊕ B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).

These dual 4-input positive-NAND gates are designed for 2V to 5.5V VCC operation. These dual 4-input positive-NAND gates are designed for 2V to 5.5V VCC operation.

These dual 4-input positive-AND gates are designed for 2-V to 5.5-V V CC operation. The SN74LV21A devices perform the Boolean function Y = A • B • C • D in positive logic. These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. These dual 4-input positive-AND gates are designed for 2-V to 5.5-V V CC operation. The SN74LV21A devices perform the Boolean function Y = A • B • C • D in positive logic. These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

The SN74LV221A is a dual multivibrator designed for 2-V to 5.5-V VCCoperation. Each multivibrator has a negative-transition-triggered (A) input and a positive-transition-triggered (B) input, either of which can be used as an inhibit input. This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, theAinput is low and the B input goes high. In the second method, the B input is high and theAinput goes low. In the third method, theAinput is low, the B input is high, and the clear (CLR) input goes high. The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cextand Rext/Cext(positive) and an external resistor connected between Rext/Cextand VCC. To obtain variable pulse durations, connect an external variable resistor between Rext/Cextand VCC. The output pulse duration also can be reduced by takingCLRlow. Pulse triggering occurs at a particular voltage level and is not related directly to the transition time of the input pulse. TheA, B, andCLRinputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. Once triggered, the outputs are independent of further transitions of theAand B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering and clearing sequences are illustrated in the input/output timing diagram. The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the SN74LV221A-Q1 is shown in Figure 8. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 5. During power up, Q outputs are in the low state, andQoutputs are in the high state. The outputs are glitch free, without applying a reset pulse. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. Pin assignments are identical to those of the SN74AHC123A and SN74AHCT123A devices, so the SN74LV221A-Q1 can be substituted for those devices not using the retrigger feature. For additional application information on multivibrators, see the application reportDesigning With The SN74AHC123A and SN74AHCT123A, literature number SCLA014. The SN74LV221A is a dual multivibrator designed for 2-V to 5.5-V VCCoperation. Each multivibrator has a negative-transition-triggered (A) input and a positive-transition-triggered (B) input, either of which can be used as an inhibit input. This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method, theAinput is low and the B input goes high. In the second method, the B input is high and theAinput goes low. In the third method, theAinput is low, the B input is high, and the clear (CLR) input goes high. The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cextand Rext/Cext(positive) and an external resistor connected between Rext/Cextand VCC. To obtain variable pulse durations, connect an external variable resistor between Rext/Cextand VCC. The output pulse duration also can be reduced by takingCLRlow. Pulse triggering occurs at a particular voltage level and is not related directly to the transition time of the input pulse. TheA, B, andCLRinputs have Schmitt triggers with sufficient hysteresis to handle slow input transition rates with jitter-free triggering at the outputs. Once triggered, the outputs are independent of further transitions of theAand B inputs and are a function of the timing components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration relative to the output pulse. Output pulse duration can be varied by choosing the appropriate timing components. Output rise and fall times are TTL compatible and independent of pulse duration. Typical triggering and clearing sequences are illustrated in the input/output timing diagram. The variance in output pulse duration from device to device typically is less than ±0.5% for given external timing components. An example of this distribution for the SN74LV221A-Q1 is shown in Figure 8. Variations in output pulse duration versus supply voltage and temperature are shown in Figure 5. During power up, Q outputs are in the low state, andQoutputs are in the high state. The outputs are glitch free, without applying a reset pulse. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. Pin assignments are identical to those of the SN74AHC123A and SN74AHCT123A devices, so the SN74LV221A-Q1 can be substituted for those devices not using the retrigger feature. For additional application information on multivibrators, see the application reportDesigning With The SN74AHC123A and SN74AHCT123A, literature number SCLA014.

These octal buffers/drivers with inverted outputs are designed for 2V to 5.5V VCC operation. The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. These octal buffers/drivers with inverted outputs are designed for 2V to 5.5V VCC operation. The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

The SN74LV244A-Q1 octal buffers and line drivers are designed for 2 V to 5.5 V VCCoperation. The device is configured into two banks of four drivers, each controlled by its own output enable pin. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The SN74LV244A-Q1 octal buffers and line drivers are designed for 2 V to 5.5 V VCCoperation. The device is configured into two banks of four drivers, each controlled by its own output enable pin. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A inputs to the Y outputs. WhenOEis high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A inputs to the Y outputs. WhenOEis high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LV244B-EP octal buffers and line drivers are designed for 2 V to 5.5 V V CC operation. The device is configured into two banks of four drivers, each controlled by its own output enable pin. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The SN74LV244B-EP octal buffers and line drivers are designed for 2 V to 5.5 V V CC operation. The device is configured into two banks of four drivers, each controlled by its own output enable pin. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This octal bus transceiver is designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements. The SN74LV245AT allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.