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SN74LV1T02-Q1

SN74LV1T02-Q1 Series

Automotive, single power supply, 2-input positive-NOR gate with logic-level shifter

Manufacturer: Texas Instruments

Catalog

Automotive, single power supply, 2-input positive-NOR gate with logic-level shifter

Key Features

AEC-Q100 qualified for automotive applications:Device temperature grade 1: -40°C to +125°CDevice HBM ESD classification level 2Device CDM ESD classification level C4BWide operating range of 1.8V to 5.5VSingle-supply voltage translator (refer to LVxT Enhanced Input Voltage):Up translation:1.2V to 1.8V1.5V to 2.5V1.8V to 3.3V3.3V to 5.0VDown translation:5.0V, 3.3V, 2.5V to 1.8V5.0V, 3.3V to 2.5V5.0V to 3.3V5.5V tolerant input pinsSupports standard pinoutsUp to 150Mbps with 5V or 3.3V VCCLatch-up performance exceeds 250mAper JESD 17AEC-Q100 qualified for automotive applications:Device temperature grade 1: -40°C to +125°CDevice HBM ESD classification level 2Device CDM ESD classification level C4BWide operating range of 1.8V to 5.5VSingle-supply voltage translator (refer to LVxT Enhanced Input Voltage):Up translation:1.2V to 1.8V1.5V to 2.5V1.8V to 3.3V3.3V to 5.0VDown translation:5.0V, 3.3V, 2.5V to 1.8V5.0V, 3.3V to 2.5V5.0V to 3.3V5.5V tolerant input pinsSupports standard pinoutsUp to 150Mbps with 5V or 3.3V VCCLatch-up performance exceeds 250mAper JESD 17

Description

AI
The SN74LV1T02-Q1 is a 2-input NOR Gate. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output). The SN74LV1T02-Q1 is a 2-input NOR Gate. Each gate performs the Boolean function Y = A + B in positive logic. The output level is referenced to the supply voltage (VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels. The input is designed with a lower threshold circuit to support up translation for lower voltage CMOS inputs (for example, 1.2V input to 1.8V output or 1.8V input to 3.3V output). In addition, the 5V tolerant input pins enable down translation (for example, 3.3V to 2.5V output).