Catalog
Parallel-load eight-bit shift registers
Key Features
• VCCoperation of 2 V to 5.5 VMaximum tpdof 10.5 ns at 5 VSupport mixed-mode voltage operation on all portsIoffsupports partial-power-down mode operationLatch-up performance exceeds 250 mA per JESD 17VCCoperation of 2 V to 5.5 VMaximum tpdof 10.5 ns at 5 VSupport mixed-mode voltage operation on all portsIoffsupports partial-power-down mode operationLatch-up performance exceeds 250 mA per JESD 17
Description
AI
The SN74LV165A device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V VCCoperation.
When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output,QH.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The SN74LV165A device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V VCCoperation.
When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’LV165A devices feature a clock-inhibit function and a complemented serial output,QH.
This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
