SN74LVC2G240 Series

2-ch, 1.65-V to 5.5-V inverters with 3-state outputs

Catalog

2-ch, 1.65-V to 5.5-V inverters with 3-state outputs

Part	Output Type	Logic Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Package / Case	Supplier Device Package [y]	Supplier Device Package	Supplier Device Package [x]	Current - Output High, Low [y]	Current - Output High, Low [x]	Number of Bits per Element	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Number of Elements	Package / Case [y]	Package / Case [y]
Texas Instruments SN74LVC2G240YEPR	3-State	Buffer Inverting	5.5 V	1.65 V	8-XFBGA DSBGA	0.9	8-DSBGA (1.9x0.9)	1.9	32 mA	32 mA	1	-40 °C	125 °C	Surface Mount	2
Texas Instruments 74LVC2G240DCURE4	3-State	Buffer Inverting	5.5 V	1.65 V	8-VFSOP				32 mA	32 mA	1	-40 °C	125 °C	Surface Mount	2	2.3 mm	0.091 in
Texas Instruments SN74LVC2G240YEAR	3-State	Buffer Inverting	5.5 V	1.65 V	8-XFBGA DSBGA		8-XFBGA DSBGA		32 mA	32 mA	1	-40 °C	125 °C	Surface Mount	2
Texas Instruments SN74LVC2G240YZAR	3-State	Buffer Inverting	5.5 V	1.65 V	8-XFBGA DSBGA	0.9	8-DSBGA (1.9x0.9)	1.9	32 mA	32 mA	1	-40 °C	125 °C	Surface Mount	2
Texas Instruments SN74LVC2G240DCUR	3-State	Buffer Inverting	5.5 V	1.65 V	8-VFSOP				32 mA	32 mA	1	-40 °C	125 °C	Surface Mount	2	2.3 mm	0.091 in
Texas Instruments SN74LVC2G240DCTR	3-State	Buffer Inverting	5.5 V	1.65 V			SM8		32 mA	32 mA	1	-40 °C	125 °C	Surface Mount	2

Catalog

2-ch, 1.65-V to 5.5-V inverters with 3-state outputs

Key Features

• Available in the Texas Instruments NanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.6 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial-Power-Down Mode, and Back-Drive ProtectionCan Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the VCCLevelLatch-Up Performance Exceeds 100 mA PerJESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)1000-V Charged-Device Model (C101)Available in the Texas Instruments NanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.6 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial-Power-Down Mode, and Back-Drive ProtectionCan Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the VCCLevelLatch-Up Performance Exceeds 100 mA PerJESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)1000-V Charged-Device Model (C101)

Description

This dual buffer driver is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A input to the Y output. WhenOEis high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This dual buffer driver is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A input to the Y output. WhenOEis high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.