SN74LVC2G132 Series

2-ch, 2-input, 1.65-V to 5.5-V NAND gates with Schmitt-Trigger inputs

Catalog

2-ch, 2-input, 1.65-V to 5.5-V NAND gates with Schmitt-Trigger inputs

Part	Operating Temperature [Max]	Operating Temperature [Min]	Number of Circuits	Package / Case [y]	Package / Case	Package / Case [y]	Current - Output High, Low [y]	Current - Output High, Low [x]	Logic Type	Number of Inputs	Features	Mounting Type	Input Logic Level - Low [Min]	Input Logic Level - Low [Max]	Current - Quiescent (Max) [Max]	Voltage - Supply [Max]	Voltage - Supply [Min]	Max Propagation Delay @ V, Max CL	Input Logic Level - High [Min]	Input Logic Level - High [Max]	Supplier Device Package	Supplier Device Package [y]	Supplier Device Package [x]
Texas Instruments SN74LVC2G132DCUT	125 °C	-40 °C	2	2.3 mm	8-VFSOP	0.091 in	32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V
Texas Instruments SN74LVC2G132DCTR	125 °C	-40 °C	2				32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V	SM8
Texas Instruments SN74LVC2G132DCUR	125 °C	-40 °C	2	2.3 mm	8-VFSOP	0.091 in	32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V
Texas Instruments SN74LVC2G132YEPR	85 °C	-40 °C	2		8-XFBGA DSBGA		32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V	8-DSBGA (1.9x0.9)	0.9	1.9
Texas Instruments 74LVC2G132DCTRG4	125 °C	-40 °C	2				32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	6 ns	1.16 V	3.33 V	SM8
Texas Instruments 74LVC2G132DCUTG4	125 °C	-40 °C	2	2.3 mm	8-VFSOP	0.091 in	32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	6 ns	1.16 V	3.33 V
Texas Instruments 74LVC2G132DCURG4	125 °C	-40 °C	2	2.3 mm	8-VFSOP	0.091 in	32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	6 ns	1.16 V	3.33 V
Texas Instruments SN74LVC2G132YZPR	85 °C	-40 °C	2		8-XFBGA DSBGA		32 mA	32 mA	NAND Gate	2	Schmitt Trigger	Surface Mount	0.39 V	1.87 V	10 µA	5.5 V	1.65 V	5 ns	1.16 V	3.33 V	8-DSBGA

Catalog

2-ch, 2-input, 1.65-V to 5.5-V NAND gates with Schmitt-Trigger inputs

Key Features

• Available in Texas Instruments NanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 5.3 ns at 3.3 VLow Power Consumption, 10-μA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial Power Down Mode, and Back Drive ProtectionSupport Translation Down (5V to 3.3V and 3.3V to 1.8V)Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Available in Texas Instruments NanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 5.3 ns at 3.3 VLow Power Consumption, 10-μA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot) >2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial Power Down Mode, and Back Drive ProtectionSupport Translation Down (5V to 3.3V and 3.3V to 1.8V)Latch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC2G132 contains two inverters and performs the Boolean function Y =A ⋅ Bor Y =A+Bin positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC2G132 contains two inverters and performs the Boolean function Y =A ⋅ Bor Y =A+Bin positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.