SN74LVC2G125 Series

2-ch, 1.65-V to 5.5-V buffers with 3-state outputs

Catalog

2-ch, 1.65-V to 5.5-V buffers with 3-state outputs

Part	Number of Bits per Element	Mounting Type	Output Type	Operating Temperature [Min]	Operating Temperature [Max]	Number of Elements	Voltage - Supply [Max]	Voltage - Supply [Min]	Logic Type	Current - Output High, Low [y]	Current - Output High, Low [x]	Package / Case [y]	Package / Case	Package / Case [y]	Supplier Device Package [y]	Supplier Device Package	Supplier Device Package [x]
Texas Instruments 74LVC2G125DCUTG4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments 74LVC2G125DCURG4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments 74LVC2G125DCURE4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments SN74LVC2G125DCUR	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments SN74LVC2G125YEPR	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA		8-XFBGA DSBGA		0.9	8-DSBGA (1.9x0.9)	1.9
Texas Instruments 74LVC2G125DCTRE4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA					SM8
Texas Instruments SN74LVC2G125DCUR-S	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in
Texas Instruments SN74LVC2G125DCT3	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA					SM8
Texas Instruments 74LVC2G125DCTR-P2	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA					SM8
Texas Instruments 74LVC2G125DCUTE4	1	Surface Mount	3-State	-40 °C	125 °C	2	5.5 V	1.65 V	Buffer Non-Inverting	32 mA	32 mA	2.3 mm	8-VFSOP	0.091 in

Catalog

2-ch, 1.65-V to 5.5-V buffers with 3-state outputs

Key Features

• ESD Protection Exceeds JESD 222000-V Human-Body Model1000-V Charged-Device ModelAvailable in the Texas InstrumentsNanoFree™ PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.3 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce)< 0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)> 2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial-Power-Down Mode, and Back-Drive ProtectionCan Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Downto the VCCLevelLatch-Up Performance Exceeds 100 mA PerJESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model1000-V Charged-Device ModelAvailable in the Texas InstrumentsNanoFree™ PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VMax tpdof 4.3 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VTypical VOLP(Output Ground Bounce)< 0.8 V at VCC= 3.3 V, TA= 25°CTypical VOHV(Output VOHUndershoot)> 2 V at VCC= 3.3 V, TA= 25°CIoffSupports Live Insertion, Partial-Power-Down Mode, and Back-Drive ProtectionCan Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Downto the VCCLevelLatch-Up Performance Exceeds 100 mA PerJESD 78, Class II

Description

The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCCoperation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCCoperation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.