Texas Instruments

This decoder is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G29 device is a 2-of-3 decoder/demultiplexer. When the enable (G) input signal is low, only one of the outputs is in the low state, depending on the input levels of A0 and A1. WhenGis high, Y0, Y1, and Y2 are high, regardless of the input states. This device is fuly specified for partial-power-down applications using Ioff. The Ioffcircuitry disable the outputs, preventing damaging current backflow through the device when it is powered down. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This decoder is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G29 device is a 2-of-3 decoder/demultiplexer. When the enable (G) input signal is low, only one of the outputs is in the low state, depending on the input levels of A0 and A1. WhenGis high, Y0, Y1, and Y2 are high, regardless of the input states. This device is fuly specified for partial-power-down applications using Ioff. The Ioffcircuitry disable the outputs, preventing damaging current backflow through the device when it is powered down. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This single channel single-pole double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3157 device can handle both analog and digital signals. The SN74LVC1G3157 device permits signals with amplitudes of up to VCC(peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. This single channel single-pole double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3157 device can handle both analog and digital signals. The SN74LVC1G3157 device permits signals with amplitudes of up to VCC(peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

The SN74LVC1G3157-Q1 device is a single-pole double-throw (SPDT) analog switch designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3157 device can handle analog and digital signals. The device permits signals with amplitudes of up to VCC(peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems. The SN74LVC1G3157-Q1 device is a single-pole double-throw (SPDT) analog switch designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3157 device can handle analog and digital signals. The device permits signals with amplitudes of up to VCC(peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G32 device performs the Boolean function Y = A + B or Y =A\ + B\in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range. The SN74LVC1G32 device is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 × 0.8 mm. This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G32 device performs the Boolean function Y = A + B or Y =A\ + B\in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCoperating range. The SN74LVC1G32 device is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 × 0.8 mm.

This device is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3208 device is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ● C in positive logic. By tying one input to GND or VCC, the SN74LVC1G3208 device offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ● C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ● C). NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This device is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3208 device is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ● C in positive logic. By tying one input to GND or VCC, the SN74LVC1G3208 device offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ● C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ● C). NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This device is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3208-Q1 is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ⋅ C in positive logic. By tying one input to GND or VCC, the SN74LVC1G3208-Q1 offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ⋅ C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ⋅ C). This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This device is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G3208-Q1 is a single 3-input positive OR-AND gate. It performs the Boolean function Y = (A + B) ⋅ C in positive logic. By tying one input to GND or VCC, the SN74LVC1G3208-Q1 offers two more functions. When C is tied to VCC, this device performs as a 2-input OR gate (Y = A + B). When A is tied to GND, the device works as a 2-input AND gate (Y = B ⋅ C). This device also works as a 2-input AND gate when B is tied to GND (Y = A ⋅ C). This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LVC1G332 device performs the Boolean function in positive logic. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The SN74LVC1G332 device performs the Boolean function in positive logic. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single buffer gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G34 device performs the Boolean function Y = A in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCOperating range. The SN74LVC1G34 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm. This single buffer gate is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G34 device performs the Boolean function Y = A in positive logic. The CMOS device has high output drive while maintaining low static power dissipation over a broad VCCOperating range. The SN74LVC1G34 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

The SN74LVC1G373 device is a single D-type latch designed for 1.65-V to 5.5-V VCCoperation. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. OEdoes not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. The SN74LVC1G373 device is a single D-type latch designed for 1.65-V to 5.5-V VCCoperation. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. OEdoes not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

This single D-type latch is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input. A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OEdoes not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This single D-type latch is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G374 features a 3-state output designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. On the positive transition of the clock (CLK) input, the Q output is set to the logic level set up at the data (D) input. A buffered output-enable (OE) input can be used to place the output in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the output neither loads nor drives the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OEdoes not affect the internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshould be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.