SN74LVC1G0832 Series

Single 3-Input Positive AND-OR Gate

Catalog

Single 3-Input Positive AND-OR Gate

Part	Number of Circuits	Package / Case	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Logic Type	Number of Inputs [custom]	Number of Inputs [custom]	Number of Inputs [custom]	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low [y]	Current - Output High, Low [x]	Mounting Type	Supplier Device Package
Texas Instruments SN74LVC1G0832DCKT	1	6-TSSOP SC-88 SOT-363	Single-Ended	85 °C	-40 °C	AND/OR Gate	3	2	1	5.5 V	1.65 V	32 mA	32 mA	Surface Mount	SC-70-6
Texas Instruments SN74LVC1G0832YEPR	1	6-XFBGA DSBGA	Single-Ended	85 °C	-40 °C	AND/OR Gate	3	2	1	5.5 V	1.65 V	32 mA	32 mA	Surface Mount	6-DSBGA
Texas Instruments SN74LVC1G0832DCKR	1	6-TSSOP SC-88 SOT-363	Single-Ended	85 °C	-40 °C	AND/OR Gate	3	2	1	5.5 V	1.65 V	32 mA	32 mA	Surface Mount	SC-70-6
Texas Instruments SN74LVC1G0832YZPR	1	6-XFBGA DSBGA	Single-Ended	85 °C	-40 °C	AND/OR Gate	3	2	1	5.5 V	1.65 V	32 mA	32 mA	Surface Mount	6-DSBGA
Texas Instruments SN74LVC1G0832DBVT	1	SOT-23-6	Single-Ended	85 °C	-40 °C	AND/OR Gate	3	2	1	5.5 V	1.65 V	32 mA	32 mA	Surface Mount	SOT-23-6
Texas Instruments SN74LVC1G0832DBVR	1	SOT-23-6	Single-Ended	85 °C	-40 °C	AND/OR Gate	3	2	1	5.5 V	1.65 V	32 mA	32 mA	Surface Mount	SOT-23-6

Catalog

Single 3-Input Positive AND-OR Gate

Key Features

• Available in the Texas Instruments NanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VProvides Down Translation to VCCMax tpdof 5 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VInput Hysteresis Allows Slow InputTransition and Better Switching NoiseImmunity at the Input(Vhys= 250 mV Typ @ 3.3 V)Can Be Used in Three Combinations:AND-OR GateAND GateOR GateIoffSupports Live Insertion, Partial-Power-Down Mode, and Back-Drive ProtectionLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Available in the Texas Instruments NanoFree PackageSupports 5-V VCCOperationInputs Accept Voltages to 5.5 VProvides Down Translation to VCCMax tpdof 5 ns at 3.3 VLow Power Consumption, 10-µA Max ICC±24-mA Output Drive at 3.3 VInput Hysteresis Allows Slow InputTransition and Better Switching NoiseImmunity at the Input(Vhys= 250 mV Typ @ 3.3 V)Can Be Used in Three Combinations:AND-OR GateAND GateOR GateIoffSupports Live Insertion, Partial-Power-Down Mode, and Back-Drive ProtectionLatch-Up Performance Exceeds 100 mA Per JESD 78, Class IIESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This device is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic. By tying one input to GND or VCC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to VCC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to VCC(Y = A + C). NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This device is designed for 1.65-V to 5.5-V VCCoperation. The SN74LVC1G0832 device is a single 3-input positive AND-OR gate. It performs the Boolean function Y = (A • B ) + C in positive logic. By tying one input to GND or VCC, the SN74LVC1G0832 device offers two more functions. When C is tied to GND, this device performs as a 2−input AND gate (Y = A • B). When A is tied to VCC, the device works as a 2−input OR gate (Y = B + C). This device also works as a 2−input OR gate when B is tied to VCC(Y = A + C). NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.