SN74LV21A Series

2-ch, 4-input 2-V to 5.5-V high-speed (7 ns) AND gate

Catalog

2-ch, 4-input 2-V to 5.5-V high-speed (7 ns) AND gate

Part	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Number of Inputs	Current - Quiescent (Max) [Max]	Number of Circuits	Input Logic Level - High	Input Logic Level - Low	Package / Case [custom]	Package / Case [custom]	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Mounting Type	Logic Type	Max Propagation Delay @ V, Max CL	Package / Case [x]	Package / Case [y]
Texas Instruments SN74LV21APWRG4	14-TSSOP	85 °C	-40 °C	4	20 µA	2	1.5 V	0.5 V	0.173 "	4.4 mm	14-TSSOP	5.5 V	2 V	12 mA	12 mA	Surface Mount	AND Gate	7 ns
Texas Instruments SN74LV21ANSR	14-SO	85 °C	-40 °C	4	20 µA	2	1.5 V	0.5 V			14-SOIC	5.5 V	2 V	12 mA	12 mA	Surface Mount	AND Gate	7 ns	0.209 "	5.3 mm
Texas Instruments SN74LV21APW	14-TSSOP	85 °C	-40 °C	4	20 µA	2	1.5 V	0.5 V	0.173 "	4.4 mm	14-TSSOP	5.5 V	2 V	12 mA	12 mA	Surface Mount	AND Gate	7 ns
Texas Instruments SN74LV21APWR	14-TSSOP	85 °C	-40 °C	4	20 µA	2	1.5 V	0.5 V	0.173 "	4.4 mm	14-TSSOP	5.5 V	2 V	12 mA	12 mA	Surface Mount	AND Gate	7 ns
Texas Instruments SN74LV21APWT	14-TSSOP	85 °C	-40 °C	4	20 µA	2	1.5 V	0.5 V	0.173 "	4.4 mm	14-TSSOP	5.5 V	2 V	12 mA	12 mA	Surface Mount	AND Gate	7 ns
Texas Instruments SN74LV21ADE4		85 °C	-40 °C	4	20 µA	2	1.5 V	0.5 V			14-SOIC	5.5 V	2 V	12 mA	12 mA	Surface Mount	AND Gate	7 ns	0.154 in	3.9 mm
Texas Instruments SN74LV21ADGVR		85 °C	-40 °C	4	20 µA	2	1.5 V	0.5 V			14-TFSOP	5.5 V	2 V	12 mA	12 mA	Surface Mount	AND Gate	7 ns	0.173 in 4.4 mm

Catalog

2-ch, 4-input 2-V to 5.5-V high-speed (7 ns) AND gate

Key Features

• 2-V to 5.5-V V CC OperationMax t pd of 6 ns at 5 VTypical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°CTypical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°CI off Supports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class II2-V to 5.5-V V CC OperationMax t pd of 6 ns at 5 VTypical V OLP (Output Ground Bounce) <0.8 V at V CC = 3.3 V, T A = 25°CTypical V OHV (Output V OH Undershoot) >2.3 V at V CC = 3.3 V, TA = 25°CI off Supports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 100 mA Per JESD 78, Class II

Description

These dual 4-input positive-AND gates are designed for 2-V to 5.5-V V CC operation. The SN74LV21A devices perform the Boolean function Y = A • B • C • D in positive logic. These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. These dual 4-input positive-AND gates are designed for 2-V to 5.5-V V CC operation. The SN74LV21A devices perform the Boolean function Y = A • B • C • D in positive logic. These devices are fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.