SN74LV240A Series

8-ch, 2V to 5.5V inverters with 3-state outputs

Catalog

8-ch, 2V to 5.5V inverters with 3-state outputs

Part	Voltage - Supply [Max]	Voltage - Supply [Min]	Output Type	Number of Elements	Mounting Type	Operating Temperature [Min]	Operating Temperature [Max]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case [y]	Package / Case	Package / Case [x]	Logic Type	Supplier Device Package	Number of Bits per Element	Package / Case [y]
Texas Instruments SN74LV240APW	5.5 V	2 V	3-State	2	Surface Mount	-40 °C	125 °C	16 mA	16 mA	4.4 mm	20-TSSOP	0.173 in	Buffer Inverting	20-TSSOP	4
Texas Instruments SN74LV240ADW	5.5 V	2 V	3-State	2	Surface Mount	-40 °C	125 °C	16 mA	16 mA	0.295 in	20-SOIC		Buffer Inverting	20-SOIC	4	7.5 mm
Texas Instruments SN74LV240APWR	5.5 V	2 V	3-State	2	Surface Mount	-40 °C	125 °C	16 mA	16 mA	4.4 mm	20-TSSOP	0.173 in	Buffer Inverting	20-TSSOP	4
Texas Instruments SN74LV240DWR
Texas Instruments SN74LV240APWRG4	5.5 V	2 V	3-State	2	Surface Mount	-40 °C	125 °C	16 mA	16 mA	4.4 mm	20-TSSOP	0.173 in	Buffer Inverting	20-TSSOP	4
Texas Instruments SN74LV240ADGVR	5.5 V	2 V	3-State	2	Surface Mount	-40 °C	125 °C	16 mA	16 mA	0.173 in	20-TFSOP		Buffer Inverting	20-TVSOP	4	4.4 mm
Texas Instruments SN74LV240APWT	5.5 V	2 V	3-State	2	Surface Mount	-40 °C	125 °C	16 mA	16 mA	4.4 mm	20-TSSOP	0.173 in	Buffer Inverting	20-TSSOP	4

Catalog

8-ch, 2V to 5.5V inverters with 3-state outputs

Key Features

• VCC operation of 2V to 5.5VMax tpd of 6.5ns at 5VTypical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°CTypical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°CSupport mixed-mode voltage operation on all portsLatch-up performance exceeds 250mA per JESD 17Ioff supports live insertion, partial power-down mode, and back drive protectionVCC operation of 2V to 5.5VMax tpd of 6.5ns at 5VTypical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°CTypical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°CSupport mixed-mode voltage operation on all portsLatch-up performance exceeds 250mA per JESD 17Ioff supports live insertion, partial power-down mode, and back drive protection

Description

These octal buffers/drivers with inverted outputs are designed for 2V to 5.5V VCC operation. The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. These octal buffers/drivers with inverted outputs are designed for 2V to 5.5V VCC operation. The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.