SN74LV244AT Series

8-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Catalog

8-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Part	Logic Type	Mounting Type	Output Type	Operating Temperature [Min]	Operating Temperature [Max]	Number of Elements	Supplier Device Package	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Bits per Element	Package / Case	Package / Case	Package / Case	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Package / Case [y]	Package / Case [x]	Package / Case [y]
Texas Instruments SN74LV244ANSR	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	125 °C	2	20-SO	5.5 V	2 V	4	20-SOIC	0.209 "	5.3 mm	16 mA	16 mA
Texas Instruments SN74LV244ADBRE4	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	125 °C	2	20-SSOP	5.5 V	2 V	4	20-SSOP			16 mA	16 mA
Texas Instruments SN74LV244ATPW	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	85 °C	2	20-TSSOP	5.5 V	4.5 V	4	20-TSSOP			16 mA	16 mA	4.4 mm	0.173 in
Texas Instruments SN74LV244ARGYR	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	125 °C	2	20-VQFN (3.5x4.5)	5.5 V	2 V	4	20-VFQFN Exposed Pad			16 mA	16 mA
Texas Instruments SN74LV244ATDGVRE4	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	85 °C	2	20-TVSOP	5.5 V	4.5 V	4	20-TFSOP			16 mA	16 mA	0.173 in		4.4 mm
Texas Instruments SN74LV244ADWE4	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	125 °C	2	20-SOIC	5.5 V	2 V	4	20-SOIC			16 mA	16 mA	0.295 in		7.5 mm
Texas Instruments SN74LV244ADW	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	125 °C	2	20-SOIC	5.5 V	2 V	4	20-SOIC			16 mA	16 mA	0.295 in		7.5 mm
Texas Instruments SN74LV244ADBR	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	125 °C	2	20-SSOP	5.5 V	2 V	4	20-SSOP			16 mA	16 mA
Texas Instruments SN74LV244ATDWR	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	85 °C	2	20-SOIC	5.5 V	4.5 V	4	20-SOIC			16 mA	16 mA	0.295 in		7.5 mm
Texas Instruments SN74LV244APWRE4	Buffer Non-Inverting	Surface Mount	3-State	-40 °C	125 °C	2	20-TSSOP	5.5 V	2 V	4	20-TSSOP			16 mA	16 mA	4.4 mm	0.173 in

Catalog

8-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs

Key Features

• Inputs Are TTL-Voltage Compatible4.5-V to 5.5-V VCCOperationTypical tpd= 5.4 ns at 5 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 5 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2.3 V at VCC= 5 V, TA= 25°CSupports Mixed-Mode Voltage Operation on All PortsIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)Inputs Are TTL-Voltage Compatible4.5-V to 5.5-V VCCOperationTypical tpd= 5.4 ns at 5 VTypical VOLP(Output Ground Bounce)<0.8 V at VCC= 5 V, TA= 25°CTypical VOHV(Output VOHUndershoot)>2.3 V at VCC= 5 V, TA= 25°CSupports Mixed-Mode Voltage Operation on All PortsIoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 250 mA Per JESD 17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)1000-V Charged-Device Model (C101)

Description

This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A inputs to the Y outputs. WhenOEis high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This octal buffer/driver is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters. The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. WhenOEis low, the device passes data from the A inputs to the Y outputs. WhenOEis high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down,OEshall be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.