SN74HCS594-Q1Eight-bit shift registers with Schmitt-trigger inputs and with output registers | Logic | 6 | Active | The SN74HCS594-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel outputs. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided for both the shift and storage register. A serial output (Q H’) is provided for cascading.
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register is one count pulse ahead of the storage register.
The SN74HCS594-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel outputs. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided for both the shift and storage register. A serial output (Q H’) is provided for cascading.
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register is one count pulse ahead of the storage register. |
SN74HCS595-Q1Automotive 8-bit shift register with Schmitt-trigger inputs and 3-state output registers | Integrated Circuits (ICs) | 8 | Active | The SN74HCS595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-trigger architecture, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the storage register outputs are in a high-impedance state. Internal register data and serial output (QH’) are not impacted by the operation of theOEinput.
The SN74HCS595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-trigger architecture, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the storage register outputs are in a high-impedance state. Internal register data and serial output (QH’) are not impacted by the operation of theOEinput. |
SN74HCS596-Q1Automotive 8-bit serial-in/parallel-out shift register | Shift Registers | 4 | Active | The SN74HCS596-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a high-impedance state. Internal register data is not impacted by the operation of theOEinput.
The SN74HCS596-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel open-drain outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the outputs are in a high-impedance state. Internal register data is not impacted by the operation of theOEinput. |
SN74HCS7002-Q1Automotive 4-ch, 2-input, 2-V to 6-V low power NOR gates with Schmitt-Trigger inputs | Logic | 2 | Active | This device contains four independent 2-input NOR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A + Bin positive logic.
This device contains four independent 2-input NOR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A + Bin positive logic. |
SN74HCS72-Q1Automotive Schmitt-trigger input dual D-type negative-edge-triggered flip-flops w/ clear and preset | Integrated Circuits (ICs) | 1 | Active | This device contains two independent D-type negative-edge-triggered flip-flops. All inputs include Schmitt-triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q,Q) on the negative-going edge of the clock (CLK) pulse. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q,Q).
This device contains two independent D-type negative-edge-triggered flip-flops. All inputs include Schmitt-triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q,Q) on the negative-going edge of the clock (CLK) pulse. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q,Q). |
SN74HCS7266-Q1Automotive 4-ch, 2-input, 2-V to 6-V low power XNOR (exclusive NOR) gates with Schmitt-Trigger input | Gates and Inverters | 2 | Active | This device contains four independent 2-input XNOR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A ⊕ Bin positive logic.
This device contains four independent 2-input XNOR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A ⊕ Bin positive logic. |
SN74HCS74-Q1Automotive Schmitt-trigger input dual D-type positive-edge-triggered flip-flops w/ clear and preset | Logic | 4 | Active | The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q,Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q,Q).
The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q,Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q,Q). |
SN74HCS86-Q1Automotive 4-ch, 2-input, 2-V to 6-V low power XOR (exclusive OR) gates with Schmitt-Trigger inputs | Logic | 4 | Active | This device contains four independent 2-input XOR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ⊕ B in positive logic.
This device contains four independent 2-input XOR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ⊕ B in positive logic. |
SN74HCT00A4-ch, 2-input, 4.5-V to 5.5-V NAND gates with TTL-compatible CMOS inputs | Integrated Circuits (ICs) | 17 | Active | This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y =A ● Bin positive logic.
This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y =A ● Bin positive logic. |
SN74HCT02A4-ch, 2-input, 4.5-V to 5.5-V NOR gates with TTL-compatible CMOS inputs | Integrated Circuits (ICs) | 14 | Active | This device contains four independent 2-input NOR gates. Each gate performs the Boolean function Y =A + Bin positive logic.
This device contains four independent 2-input NOR gates. Each gate performs the Boolean function Y =A + Bin positive logic. |
