
SN74HCS594-Q1 Series
Eight-bit shift registers with Schmitt-trigger inputs and with output registers
Manufacturer: Texas Instruments
Catalog
Eight-bit shift registers with Schmitt-trigger inputs and with output registers
Key Features
• AEC-Q100 Qualified for automotive applications:Device temperature grade 1: –40°C to +125°C, T ADevice HBM ESD Classification Level 2Device CDM ESD Classification Level C6Available in wettable flank QFN (WBQB) packageWide operating voltage range: 2 V to 6 VSchmitt-trigger inputs allow for slow or noisy input signalsLow power consumption:Typical I CC of 100 nATypical input leakage current of ±100 nA±7.8-mA output drive at 6 VAEC-Q100 Qualified for automotive applications:Device temperature grade 1: –40°C to +125°C, T ADevice HBM ESD Classification Level 2Device CDM ESD Classification Level C6Available in wettable flank QFN (WBQB) packageWide operating voltage range: 2 V to 6 VSchmitt-trigger inputs allow for slow or noisy input signalsLow power consumption:Typical I CC of 100 nATypical input leakage current of ±100 nA±7.8-mA output drive at 6 V
Description
AI
The SN74HCS594-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel outputs. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided for both the shift and storage register. A serial output (Q H’) is provided for cascading.
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register is one count pulse ahead of the storage register.
The SN74HCS594-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. All inputs include Schmitt-triggers, eliminating any erroneous data outputs due to slow-edged or noisy input signals. The storage register has parallel outputs. Separate clocks and direct overriding clear ( SRCLR, RCLR) inputs are provided for both the shift and storage register. A serial output (Q H’) is provided for cascading.
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are connected together, the shift register is one count pulse ahead of the storage register.