SN74HCT245AHigh Speed CMOS Logic Non-Inverting Octal-Bus Transceiver with 3-State Outpus | Buffers, Drivers, Receivers, Transceivers | 19 | Active | The SNx4HCT245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The SNx4HCT245 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
The SNx4HCT245 octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
The SNx4HCT245 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated. |
SN74HCT273High Speed CMOS Logic Octal D-Type Flip-Flop with Reset | Integrated Circuits (ICs) | 13 | Active | These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock.
These devices are positive-edge-triggered D-type flip-flops with a common enable input. The ’HCT273 devices are similar to the ’HCT377 devices, but feature a common clear enable (CLR) input instead of a latched clock. |
SN74HCT32A4-ch 2-input 4.5-V to 5.5-V OR gate with TTL-compatible inputs | Logic | 17 | Active | This device contains four independent 2-input OR gates. Each gate performs the Boolean function Y = A + B in positive logic.
This device contains four independent 2-input OR gates. Each gate performs the Boolean function Y = A + B in positive logic. |
SN74HCT373AHigh Speed CMOS Logic Octal Transparent Latches with 3-State Outputs | Integrated Circuits (ICs) | 13 | Active | High Speed CMOS Logic Octal Transparent Latches with 3-State Outputs |
SN74HCT374AHigh Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State Outputs | Logic | 12 | Active | High Speed CMOS Logic Octal Positive-Edge Triggered D-Type Flip-Flops with 3-State Outputs |
SN74HCT377High Speed CMOS Logic Octal D-Type Flip-Flop with Data Enable | Flip Flops | 7 | Active | These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\.
These devices are positive-edge-triggered D-type flip-flops. The ’HCT377 devices are similar to the ’'HCT273 devices, but feature a latched clock-enable (CLKEN)\ input instead of a common clear.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock (CLK) pulse if CLKEN\ is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output. These devices are designed to prevent false clocking by transitions at CLKEN\. |
SN74HCT541A8-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs | Logic | 20 | Active | 8-ch, 4.5-V to 5.5-V buffers with TTL-compatible CMOS inputs and 3-state outputs |
SN74HCT595-Q1Automotive 8-bit shift register with TLL-compatible CMOS inputs and 3-state output registers | Logic | 1 | Active | The SN74HCT595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the storage register outputs are in a high-impedance state. Internal register data and serial output (QH’) are not impacted by the operation of theOEinput.
The SN74HCT595-Q1 device contains an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and a serial output (QH’) for cascading. When the output-enable (OE) input is high, the storage register outputs are in a high-impedance state. Internal register data and serial output (QH’) are not impacted by the operation of theOEinput. |
SN74HCT623Octal Bus Transceivers With 3-State Outputs | Integrated Circuits (ICs) | 1 | Active | These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing.
The ’HCT623 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the output-enable (OEAB and OEBA\) inputs.
The output-enable inputs disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability to store data by simultaneously enabling OEAB and OEBA\. Each output reinforces its input in this transceiver configuration. When both OEAB and OEBA\ are enabled and all other data sources to the two sets of bus lines are in the high-impedance state, both sets of bus lines (16 total) remain at their last states. The 8-bit codes appearing on the two sets of buses are identical.
To ensure the high-impedance state during power up or power down, OEBA\ should be tied to VCCthrough a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
These octal bus transceivers are designed for asynchronous two-way communication between data buses. The control-function implementation allows for maximum flexibility in timing.
The ’HCT623 devices allow data transmission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic levels at the output-enable (OEAB and OEBA\) inputs.
The output-enable inputs disable the device so that the buses are effectively isolated. The dual-enable configuration gives the transceivers the capability to store data by simultaneously enabling OEAB and OEBA\. Each output reinforces its input in this transceiver configuration. When both OEAB and OEBA\ are enabled and all other data sources to the two sets of bus lines are in the high-impedance state, both sets of bus lines (16 total) remain at their last states. The 8-bit codes appearing on the two sets of buses are identical.
To ensure the high-impedance state during power up or power down, OEBA\ should be tied to VCCthrough a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. |
SN74HCT645Octal Bus Transceivers With 3-State Outputs | Buffers, Drivers, Receivers, Transceivers | 7 | Active | These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated.
These octal bus transceivers are designed for asynchronous two-way communication between data buses. These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the level at the direction-control (DIR) input. The output-enable (OE)\ input can be used to disable the device so the buses are effectively isolated. |
