Texas Instruments

This device contains six independent inverters. Each gate performs the Boolean function Y =Ain positive logic. This device contains six independent inverters. Each gate performs the Boolean function Y =Ain positive logic.

This device contains four independent 2-input AND gates. Each gate performs the Boolean function Y = A ● B in positive logic. This device contains four independent 2-input AND gates. Each gate performs the Boolean function Y = A ● B in positive logic.

This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic. This device contains four independent buffers with 3-state outputs. Each gate performs the Boolean function Y = A in positive logic.

High Speed CMOS Logic 3-to-8 Line Decoder/Demultiplexer Inverting and Non-Inverting

The ’HC139 and ’HCT139 devices contain two independent binary to one of four decoders each with a single active low enable input (1E\ or 2E\). Data on the select inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four normally high outputs to go low. If the enable input is high all four outputs remain high. For demultiplexer operation the enable input is the data input. The enable input also functions as a chip select when these devices are cascaded. This device is functionally the same as the CD4556B and is pin compatible with it. The outputs of these devices can drive 10 low power Schottky TTL equivalent loads. The HCT logic family is functionally as well as pin equivalent to the LS logic family. The ’HC139 and ’HCT139 devices contain two independent binary to one of four decoders each with a single active low enable input (1E\ or 2E\). Data on the select inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four normally high outputs to go low. If the enable input is high all four outputs remain high. For demultiplexer operation the enable input is the data input. The enable input also functions as a chip select when these devices are cascaded. This device is functionally the same as the CD4556B and is pin compatible with it. The outputs of these devices can drive 10 low power Schottky TTL equivalent loads. The HCT logic family is functionally as well as pin equivalent to the LS logic family.

This device contains six independent inverters with Schmitt-trigger inputs. Each gate performs the Boolean function Y =Ain positive logic. This device contains six independent inverters with Schmitt-trigger inputs. Each gate performs the Boolean function Y =Ain positive logic.

The ’HC157, ’HCT157, ’HC158, and ’HCT158 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select input (S). The Enable input (E\) is active Low. When (E\) is High, all of the outputs in the 158, the inverting type, (1Y\-4Y\) are forced High and in the 157, the non-inverting type, all of the outputs (1Y\-4Y\) are forced Low, regardless of all other input conditions. Moving data from two groups of registers to four common output busses is a common use of these devices. The state of the Select input determines the particular register from which the data comes. They can also be used as function generators. The ’HC157, ’HCT157, ’HC158, and ’HCT158 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select input (S). The Enable input (E\) is active Low. When (E\) is High, all of the outputs in the 158, the inverting type, (1Y\-4Y\) are forced High and in the 157, the non-inverting type, all of the outputs (1Y\-4Y\) are forced Low, regardless of all other input conditions. Moving data from two groups of registers to four common output busses is a common use of these devices. The state of the Select input determines the particular register from which the data comes. They can also be used as function generators.

The SN74HCT165-Q1 is a parallel- or serial-in, serial-out 8-bit shift register. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HCT165-Q1 also features a clock-inhibit (CLK INH) function and a complementary serial (QH) output. The SN74HCT165-Q1 is a parallel- or serial-in, serial-out 8-bit shift register. Parallel-in access to each stage is provided by eight individual direct data (A-H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74HCT165-Q1 also features a clock-inhibit (CLK INH) function and a complementary serial (QH) output.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The ’HCT240 devices are organized as two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SNx4HCT244 devices are organized as two 4-bit buffers or drivers with separate output-enable (OE) inputs. When OE is low, the device passes non inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. The SNx4HCT244 devices are organized as two 4-bit buffers or drivers with separate output-enable (OE) inputs. When OE is low, the device passes non inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.