SN74HCS72-Q1 Series

Automotive Schmitt-trigger input dual D-type negative-edge-triggered flip-flops w/ clear and preset

Catalog

Automotive Schmitt-trigger input dual D-type negative-edge-triggered flip-flops w/ clear and preset

Part	Clock Frequency	Operating Temperature [Min]	Operating Temperature [Max]	Function	Number of Bits per Element	Current - Quiescent (Iq)	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Number of Elements	Max Propagation Delay @ V, Max CL	Output Type	Trigger Type	Input Capacitance	Voltage - Supply [Min]	Voltage - Supply [Max]	Grade	Package / Case [x]	Package / Case [y]	Package / Case	Type	Qualification	Mounting Type
Texas Instruments SN74HCS72QDRQ1	74 MHz	-40 °C	125 °C	Reset Set(Preset)	1	2 µA	7.8 mA	7.8 mA	2	15 ns	Complementary	Negative Edge	5 pF	2 V	6 V	Automotive	0.154 in	3.9 mm	14-SOIC	D-Type	AEC-Q100	Surface Mount

Catalog

Automotive Schmitt-trigger input dual D-type negative-edge-triggered flip-flops w/ clear and preset

Key Features

• AEC-Q100 Qualified for automotive applications:Device temperature grade 1: –40°C to +125°C, TADevice HBM ESD Classification Level 2Device CDM ESD Classifcation Level C6Wide operating voltage range: 2 V to 6 VSchmitt-trigger inputs allow for slow or noisy input signalsLow power consumptionTypical ICCof 100 nATypical input leakage current of ±100 nA±7.8-mA output drive at 5 VAEC-Q100 Qualified for automotive applications:Device temperature grade 1: –40°C to +125°C, TADevice HBM ESD Classification Level 2Device CDM ESD Classifcation Level C6Wide operating voltage range: 2 V to 6 VSchmitt-trigger inputs allow for slow or noisy input signalsLow power consumptionTypical ICCof 100 nATypical input leakage current of ±100 nA±7.8-mA output drive at 5 V

Description

This device contains two independent D-type negative-edge-triggered flip-flops. All inputs include Schmitt-triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q,Q) on the negative-going edge of the clock (CLK) pulse. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q,Q). This device contains two independent D-type negative-edge-triggered flip-flops. All inputs include Schmitt-triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q,Q) on the negative-going edge of the clock (CLK) pulse. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q,Q).