
SN74HCS74-Q1 Series
Automotive Schmitt-trigger input dual D-type positive-edge-triggered flip-flops w/ clear and preset
Manufacturer: Texas Instruments
Catalog
Automotive Schmitt-trigger input dual D-type positive-edge-triggered flip-flops w/ clear and preset
Key Features
• AEC-Q100 Qualified for automotive applications:Device temperature grade 1: –40°C to +125°C, TADevice HBM ESD Classification Level 2Device CDM ESD Classifcation Level C6Wide operating voltage range: 2 V to 6 VSchmitt-trigger inputs allow for slow or noisy input signalsLow power consumptionTypical ICCof 100 nATypical input leakage current of ±100 nA±7.8-mA output drive at 6 VAEC-Q100 Qualified for automotive applications:Device temperature grade 1: –40°C to +125°C, TADevice HBM ESD Classification Level 2Device CDM ESD Classifcation Level C6Wide operating voltage range: 2 V to 6 VSchmitt-trigger inputs allow for slow or noisy input signalsLow power consumptionTypical ICCof 100 nATypical input leakage current of ±100 nA±7.8-mA output drive at 6 V
Description
AI
The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q,Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q,Q).
The device contains two independent D-type positive-edge-triggered flip-flops. All inputs include Schmitt triggers, allowing for slow or noisy input signals. A low level at the preset (PRE) input sets the output high. A low level at the clear (CLR) input resets the output low. Preset and clear functions are asynchronous and not dependent on the levels of the other inputs. WhenPREandCLRare inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs (Q,Q) on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the input clock (CLK) signal. Following the hold-time interval, data at the data (D) input can be changed without affecting the levels at the outputs (Q,Q).