Texas Instruments

The SN74HCS273-Q1 device contains eight positive-edge-triggered D-type flip-flops with Schmitt-trigger inputs, shared asynchronous active low clear (CLR) input, and shared rising-edge triggered clock (CLK) input. The SN74HCS273-Q1 device contains eight positive-edge-triggered D-type flip-flops with Schmitt-trigger inputs, shared asynchronous active low clear (CLR) input, and shared rising-edge triggered clock (CLK) input.

This device contains one independent 8-input NAND gate with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A ● B ● C ● D ● E ● F ● G ● Hin positive logic. This device contains one independent 8-input NAND gate with Schmitt-trigger inputs. Each gate performs the Boolean function Y =A ● B ● C ● D ● E ● F ● G ● Hin positive logic.

This device contains four independent 2-input OR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A + B in positive logic. This device contains four independent 2-input OR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A + B in positive logic.

The SN74HCS365-Q1 contains six independent buffers with Schmitt-trigger inputs and 3-state outputs. All channels are placed into the high-impedance mode when either of the output enable (OE) pins are set to the high state. The SN74HCS365-Q1 contains six independent buffers with Schmitt-trigger inputs and 3-state outputs. All channels are placed into the high-impedance mode when either of the output enable (OE) pins are set to the high state.

The SN74HCS367-Q1 is a hex buffer with 3-state outputs and Schmitt-trigger inputs. The device is configured into two banks, one with four drivers and one with two drivers, each controlled by its own output enable pin. The SN74HCS367-Q1 is a hex buffer with 3-state outputs and Schmitt-trigger inputs. The device is configured into two banks, one with four drivers and one with two drivers, each controlled by its own output enable pin.

The SN74HCS373-Q1 contains eight D-type latches. All inputs include Schmitt-trigger architecture. All channels share a latch enable (LE) input and output enable (OE) input. The SN74HCS373-Q1 contains eight D-type latches. All inputs include Schmitt-trigger architecture. All channels share a latch enable (LE) input and output enable (OE) input.

This device contains three independent 3-input OR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A + B + C in positive logic. This device contains three independent 3-input OR Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A + B + C in positive logic.

The SN74HCS573 contains eight D-type latches. All inputs include Schmitt-trigger architecture. All channels share a latch enable (LE) input and output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing. The SN74HCS573 contains eight D-type latches. All inputs include Schmitt-trigger architecture. All channels share a latch enable (LE) input and output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.

The SN74HCS574 contains eight D-type flip-flops. All inputs include Schmitt-trigger architecture. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing. The SN74HCS574 contains eight D-type flip-flops. All inputs include Schmitt-trigger architecture. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.

The SN74HCS574-Q1 contains eight D-type flip-flops. All inputs include Schmitt-trigger architecture. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing. The SN74HCS574-Q1 contains eight D-type flip-flops. All inputs include Schmitt-trigger architecture. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.