SN65DP14112-Gbps DP 1.4/ eDP1.4 linear redriver | Linear | 2 | Active | The SN65DP141 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for use up to 12 Gbps and compensates for losses due to board traces and cables.
The device is transparent to DisplayPort (DP) link training such a way that a DP source and a sink can perform effective link training overcoming traditionalaux snoopingre-drivers’ shortcomings. Additionally, the device is position independent. It can be placed inside source, cable or sink effectively providing anegative losscomponent to the overall link budget. Linear equalization inside SN65DP141 also increases link margin when used with a receiver implementing Decision Feedback Equalization (DFE).
SN65DP141 allows independent channel control for equalization, gain, dynamic range using both I2C and GPIO configurations.
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The SN65DP141 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for use up to 12 Gbps and compensates for losses due to board traces and cables.
The device is transparent to DisplayPort (DP) link training such a way that a DP source and a sink can perform effective link training overcoming traditionalaux snoopingre-drivers’ shortcomings. Additionally, the device is position independent. It can be placed inside source, cable or sink effectively providing anegative losscomponent to the overall link budget. Linear equalization inside SN65DP141 also increases link margin when used with a receiver implementing Decision Feedback Equalization (DFE).
SN65DP141 allows independent channel control for equalization, gain, dynamic range using both I2C and GPIO configurations.
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SN65DP1493.4-Gbps DP++ 1.1 to HDMI 1.4b retimer -40 to 85C operating temperature | Video Processing | 2 | Active | The SNx5DP149 device is a dual mode DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b output signals. The SNx5DP149 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link. The SNx5DP149 device supports data rate up to 3.4-Gbps per data lane to support Ultra HD (4K × 2K / 30-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP149 device can automatically configure itself as a re-driver at data rates <1 Gbps, or as a retimer at more than this data rate. This feature can be turned off through I2C programming.
For signal integrity, the SNx5DP149 device implements several features. The SNx5DP149 receiver supports both adaptive and fixed equalization to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. When working as a retimer, the embedded clock data recovery (CDR) cleans up the input high frequency and random jitter from video source. The transmitter provides several features for passing compliance and reducing system-level design issues like de-emphasis, which compensates for the attenuation when driving long cables or high-loss board traces. The SNx5DP149 device also includes TMDS output amplitude adjust using an external resistor on the Vsadj pin, source termination selection, and output slew rate control. Device operation and configuration can be programmed by pin strapping or I2C.
The SNx5DP149 device implements several methods for power management and active power reduction.
The SNx5DP149 receiver comes in a 40-pin RSB supporting space-constrained applications.
The SN65DP149 device is characterized for an industrial operational temperature range from –40°C to 85°C.
The SN75DP149 device is characterized for an extended commercial operational temperature range from 0°C to 85°C.
The SNx5DP149 device is a dual mode DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b output signals. The SNx5DP149 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link. The SNx5DP149 device supports data rate up to 3.4-Gbps per data lane to support Ultra HD (4K × 2K / 30-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP149 device can automatically configure itself as a re-driver at data rates <1 Gbps, or as a retimer at more than this data rate. This feature can be turned off through I2C programming.
For signal integrity, the SNx5DP149 device implements several features. The SNx5DP149 receiver supports both adaptive and fixed equalization to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. When working as a retimer, the embedded clock data recovery (CDR) cleans up the input high frequency and random jitter from video source. The transmitter provides several features for passing compliance and reducing system-level design issues like de-emphasis, which compensates for the attenuation when driving long cables or high-loss board traces. The SNx5DP149 device also includes TMDS output amplitude adjust using an external resistor on the Vsadj pin, source termination selection, and output slew rate control. Device operation and configuration can be programmed by pin strapping or I2C.
The SNx5DP149 device implements several methods for power management and active power reduction.
The SNx5DP149 receiver comes in a 40-pin RSB supporting space-constrained applications.
The SN65DP149 device is characterized for an industrial operational temperature range from –40°C to 85°C.
The SN75DP149 device is characterized for an extended commercial operational temperature range from 0°C to 85°C. |
SN65DP1596-Gbps DP++ 1.1 to HDMI 2.0 retimer -40 to 85C operating temperature | Integrated Circuits (ICs) | 3 | Active | The SNx5DP159 device is a dual mode[1] DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b and 2.0b output signals. The SNx5DP159 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link or AUX channel. The SNx5DP159 device supports data rate up to 6-Gbps per data lane to support Ultra HD (4K × 2K / 60-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP159 device can automatically configure itself as a re-driver at data rates <1 Gbps, or as a retimer at more than this data rate. This feature can be turned off through I2C[4] programming.
For signal integrity, the SNx5DP159 device implements several features. The SNx5DP159 receiver supports both adaptive and fixed equalization to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. When working as a retimer, the embedded clock data recovery (CDR) cleans up the input high frequency and random jitter from video source. The transmitter provides several features for passing compliance and reducing system-level design issues like de-emphasis, which compensates for the attenuation when driving long cables or high-loss board traces. The SNx5DP159 device also includes TMDS output amplitude adjust using an external resistor on the Vsadj pin, source termination selection, and output slew rate control. Device operation and configuration can be programmed by pin strapping or I2C[4].
The SNx5DP159 device implements several methods for power management and active power reduction.
The SNx5DP159 receiver uses several methods to determine whether the application supports HDMI1.4b[2] or HDMI2.0[3] data rates. The SNx5DP159 receiver comes in two packages: a 40-pin RSB supporting space-constrained applications and a 48-pin RGZ version supporting the full feature set for DisplayPort dual-mode standard version 1.1 in applications such as dongles.
The SN65DP159 device is characterized for an industrial operational temperature range from –40°C to 85°C.
The SN75DP159 device is characterized for an extended commercial operational temperature range from 0°C to 85°C.
The SNx5DP159 device is a dual mode[1] DisplayPort to transition-minimized differential signal (TMDS) retimer supporting digital video interface (DVI) 1.0 and high-definition multimedia interface (HDMI) 1.4b and 2.0b output signals. The SNx5DP159 device supports the dual mode standard version 1.1 type 1 and type 2 through the DDC link or AUX channel. The SNx5DP159 device supports data rate up to 6-Gbps per data lane to support Ultra HD (4K × 2K / 60-Hz) 8-bits per color high-resolution video and HDTV with 16-bit color depth at 1080p (1920 × 1080 / 60-Hz). The SNx5DP159 device can automatically configure itself as a re-driver at data rates <1 Gbps, or as a retimer at more than this data rate. This feature can be turned off through I2C[4] programming.
For signal integrity, the SNx5DP159 device implements several features. The SNx5DP159 receiver supports both adaptive and fixed equalization to clean up inter-symbol interference (ISI) jitter or loss from the bandwidth-limited board traces or cables. When working as a retimer, the embedded clock data recovery (CDR) cleans up the input high frequency and random jitter from video source. The transmitter provides several features for passing compliance and reducing system-level design issues like de-emphasis, which compensates for the attenuation when driving long cables or high-loss board traces. The SNx5DP159 device also includes TMDS output amplitude adjust using an external resistor on the Vsadj pin, source termination selection, and output slew rate control. Device operation and configuration can be programmed by pin strapping or I2C[4].
The SNx5DP159 device implements several methods for power management and active power reduction.
The SNx5DP159 receiver uses several methods to determine whether the application supports HDMI1.4b[2] or HDMI2.0[3] data rates. The SNx5DP159 receiver comes in two packages: a 40-pin RSB supporting space-constrained applications and a 48-pin RGZ version supporting the full feature set for DisplayPort dual-mode standard version 1.1 in applications such as dongles.
The SN65DP159 device is characterized for an industrial operational temperature range from –40°C to 85°C.
The SN75DP159 device is characterized for an extended commercial operational temperature range from 0°C to 85°C. |
SN65DPHY440SSMIPI® CSI-2/DSI DPHY retimer -40 to 85C operating temperature | Linear | 2 | Active | The DPHY440 is a 1-lane to 4-lane and clock MIPI DPHY retimer that regenerates the DPHY signaling. The device complies with MIPI DPHY 1.1 standard and can be used in either a MIPI CSI-2 or MIPI DSI application at datarates of up to 1.5Gbps.
The device compensates for PCB, connector, and cable related frequency loss and switching related loss to provide the optimum electrical performance from a CSI-2/DSI source to sink. The DPHY440 DPHY inputs feature configurable equalizers.
The output pins automatically compensate for uneven skew between clock and data lanes received on the inputs ports of the device. The DPHY440 output voltage swing and edge rate can be adjusted by changing the state of the VSADJ_CFG0 pin and ERC pin, respectively.
The DPHY440 is optimized for mobile applications, and contains activity detection circuitry on the DPHY Link interface that can transition into a lower power mode when in ULPS and LP states.
The SN65DPHY440SS is characterized for an industrial temperature range from –40°C to 85°C while SN75DPHY440SS is characterized for commercial temperature range from 0°C to 70°C.
The DPHY440 is a 1-lane to 4-lane and clock MIPI DPHY retimer that regenerates the DPHY signaling. The device complies with MIPI DPHY 1.1 standard and can be used in either a MIPI CSI-2 or MIPI DSI application at datarates of up to 1.5Gbps.
The device compensates for PCB, connector, and cable related frequency loss and switching related loss to provide the optimum electrical performance from a CSI-2/DSI source to sink. The DPHY440 DPHY inputs feature configurable equalizers.
The output pins automatically compensate for uneven skew between clock and data lanes received on the inputs ports of the device. The DPHY440 output voltage swing and edge rate can be adjusted by changing the state of the VSADJ_CFG0 pin and ERC pin, respectively.
The DPHY440 is optimized for mobile applications, and contains activity detection circuitry on the DPHY Link interface that can transition into a lower power mode when in ULPS and LP states.
The SN65DPHY440SS is characterized for an industrial temperature range from –40°C to 85°C while SN75DPHY440SS is characterized for commercial temperature range from 0°C to 70°C. |
SN65DSI83-Q1Automotive single-channel MIPI® DSI to single-link LVDS bridge | Evaluation Boards | 3 | Active | The SN65DSI83-Q1 DSI-to-LVDS bridge features a single-channel MIPI D-PHY receiver front-endconfiguration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.
The SN65DSI83-Q1 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83-Q1 device is also suitable for applications using 60 fps 1366 × 768/1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI83-Q1 device is implemented in a small outline 10-mm × 10-mm HTQFP package with a0.5-mm pitch, and operates across a temperature range from –40°C to +105°C.
The SN65DSI83-Q1 DSI-to-LVDS bridge features a single-channel MIPI D-PHY receiver front-endconfiguration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Single-Link LVDS with four data lanes per link.
The SN65DSI83-Q1 device can support up to WUXGA 1920 × 1200 at 60 frames per second, at 24 bpp with reduced blanking. The SN65DSI83-Q1 device is also suitable for applications using 60 fps 1366 × 768/1280 × 800 at 18 bpp and 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI83-Q1 device is implemented in a small outline 10-mm × 10-mm HTQFP package with a0.5-mm pitch, and operates across a temperature range from –40°C to +105°C. |
SN65DSI84MIPI® DSI bridge to Flatlink™ LVDS single-channel DSI to dual-link LVDS bridge | Interface | 1 | Active | The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface with four data lanes per link.
The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
Designed with industry compliant interface technology, the SN65DSI84 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.
The SN65DSI84 is implemented in a small outline 5x5mm nFBGA at 0.5 mm pitch package, and operates across a temperature range from -40°C to 85°C.
The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual-Link LVDS, Single-Link LVDS interface with four data lanes per link.
The SN65DSI84 is well suited for WUXGA 1920 x 1200 at 60 frames per second, with up to 24 bits-per-pixel. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
Designed with industry compliant interface technology, the SN65DSI84 is compatible with a wide range of micro-processors, and is designed with a range of power management features including low-swing LVDS outputs, and the MIPI® defined ultra-low power state (ULPS) support.
The SN65DSI84 is implemented in a small outline 5x5mm nFBGA at 0.5 mm pitch package, and operates across a temperature range from -40°C to 85°C. |
SN65DSI85-Q1Automotive dual-channel MIPI DSI to dual-link Flatlink™ LVDS bridge | Evaluation and Demonstration Boards and Kits | 2 | Active | The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-endconfiguration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.
The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.
The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-endconfiguration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.
The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a0.5-mm pitch, and operates across a temperature range from –40°C to 105°C. |
SN65DSI86-Q1Dual-channel MIPI® DSI to embedded DisplayPort™ (eDP ) bridge | Interface | 2 | Active | The SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.
The SN65DSI86-Q1 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.
Designed with industry compliant interface technology, the is compatible with a wide range of microprocessors, and is designed with a range of power management features, including panel refresh support, and the MIPI defined ultralow power state (ULPS) support.
The SN65DSI86 Q1 is implemented in a 10-mm × 10-mm HTQFP at 0.5-mm pitch package, and operates across a temperature range from –40°C to +85°C.
In the rest of this document, the SN65DSI86-Q1 is referred to as SN65DSIx6 or DSIx6.
The SN65DSI86-Q1 DSI to embedded DisplayPort (eDP) bridge features a dual-channel MIPI D-PHY receiver front-end configuration with four lanes per channel operating at 1.5 Gbps per lane and a maximum input bandwidth of 12 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data stream to a DisplayPort with up to four lanes at either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps, 3.24 Gbps, 4.32 Gbps, or 5.4 Gbps.
The SN65DSI86-Q1 is well suited for WQXGA at 60 frames per second, as well as 3D graphics at 4K and true HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bpp. Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and DisplayPort interfaces.
Designed with industry compliant interface technology, the is compatible with a wide range of microprocessors, and is designed with a range of power management features, including panel refresh support, and the MIPI defined ultralow power state (ULPS) support.
The SN65DSI86 Q1 is implemented in a 10-mm × 10-mm HTQFP at 0.5-mm pitch package, and operates across a temperature range from –40°C to +85°C.
In the rest of this document, the SN65DSI86-Q1 is referred to as SN65DSIx6 or DSIx6. |
| Clock/Timing | 2 | Obsolete | |
| Clock Buffers, Drivers | 1 | Active | The SN65EL11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in an open condition. The SN65EL11 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 package.
The SN65EL11 is a differential 1:2 PECL/ECL fanout buffer. The device includes circuitry to maintain a known logic level when inputs are in an open condition. The SN65EL11 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 package. |
