SN65DSI85-Q1 Series
Automotive dual-channel MIPI DSI to dual-link Flatlink™ LVDS bridge
Manufacturer: Texas Instruments
Catalog
Automotive dual-channel MIPI DSI to dual-link Flatlink™ LVDS bridge
Key Features
• Qualified for Automotive ApplicationsAEC-Q100 Qualified With the Following Results:Device Temperature Grade 2: –40°C to 105°C Ambient Operating TemperatureDevice HBM ESD Classification Level 3ADevice CDM ESD Classification Level C6Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per LaneSupports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 FormatsSuitable for 60-fps WQXGA 2560 × 1600 Resolution at 18-bpp and 24-bpp Color, and 60 fps (120 fps Equivalent) WUXGA 1920 × 1200 Resolution With 3D Graphics at 24-bpp ColorMIPI Front-End Configurable for Single-Channel or Dual-Channel DSI ConfigurationsOutput Configurable for Single-Link or Dual-Link LVDSSupports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating ModesSupports Two Single-Channel DSI to Two Single-Link LVDS Operating ModeLVDS Output-Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link ModeLVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)1.8-V Main VCCPower SupplyLow Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) SupportLVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB RoutingPackaged in 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC PackageQualified for Automotive ApplicationsAEC-Q100 Qualified With the Following Results:Device Temperature Grade 2: –40°C to 105°C Ambient Operating TemperatureDevice HBM ESD Classification Level 3ADevice CDM ESD Classification Level C6Implements MIPI D-PHY Version 1.00.00 Physical Layer Front-End and Display Serial Interface (DSI) Version 1.02.00Dual-Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per LaneSupports 18-bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 FormatsSuitable for 60-fps WQXGA 2560 × 1600 Resolution at 18-bpp and 24-bpp Color, and 60 fps (120 fps Equivalent) WUXGA 1920 × 1200 Resolution With 3D Graphics at 24-bpp ColorMIPI Front-End Configurable for Single-Channel or Dual-Channel DSI ConfigurationsOutput Configurable for Single-Link or Dual-Link LVDSSupports Dual-Channel DSI ODD or EVEN and LEFT or RIGHT Operating ModesSupports Two Single-Channel DSI to Two Single-Link LVDS Operating ModeLVDS Output-Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link ModeLVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)1.8-V Main VCCPower SupplyLow Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) SupportLVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB RoutingPackaged in 64-pin 10 mm × 10 mm HTQFP (PAP) PowerPAD™ IC Package
Description
AI
The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-endconfiguration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.
The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.
The SN65DSI85-Q1 DSI-to-LVDS bridge features a dual-channel MIPI D-PHY receiver front-endconfiguration with four lanes per channel operating at 1 Gbps per lane and a maximum input bandwidth of 8 Gbps. The bridge decodes MIPI DSI 18-bpp RGB666 and 24-bpp RGB888 packets and converts the formatted video data-stream to an LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a dual-link LVDS, single-link LVDS, or two Single-Link LVDS interfaces with four data lanes per link.
The SN65DSI85-Q1 device is well suited for WQXGA (2560 × 1600) at 60 frames per second (fps), as well as 3D Graphics at WUXGA and True HD (1920 × 1080) resolutions at an equivalent 120 fps with up to 24 bits-per-pixel (bpp). Partial line buffering is implemented to accommodate the data stream mismatch between the DSI and LVDS interfaces.
The SN65DSI85-Q1 device is implemented in a small outline 10 mm × 10 mm HTQFP package with a0.5-mm pitch, and operates across a temperature range from –40°C to 105°C.
