Texas Instruments

The LMH7322 is a dual comparator with 700 ps propagation delay, low dispersion of 75 ps and an input voltage range that extends from VCC-1.5V to VEE. The devices can be operated from a wide supply voltage range of 2.7V to 12V. The adjustable hysteresis adds flexibility and prevents oscillations. Both the outputs and latch inputs of the LMH7322 are RSPECL compatible. When used in combination with a VCCOsupply voltage of 2.5V the outputs have LVDS compatible levels. The LMH7322 is available in a 24-pin WQFN package. The LMH7322 is a dual comparator with 700 ps propagation delay, low dispersion of 75 ps and an input voltage range that extends from VCC-1.5V to VEE. The devices can be operated from a wide supply voltage range of 2.7V to 12V. The adjustable hysteresis adds flexibility and prevents oscillations. Both the outputs and latch inputs of the LMH7322 are RSPECL compatible. When used in combination with a VCCOsupply voltage of 2.5V the outputs have LVDS compatible levels. The LMH7322 is available in a 24-pin WQFN package.

The LMH9126 is high-performance, single-channel, differential input to single-ended output transmit RF gain block amplifier supporting 2.6-GHz center frequency band. The device is well suited to support requirements for the next generation 5G AAS or small cell applications while driving the input of a power amplifier (PA). The RF amplifier provides 18-dB typical gain with good linearity performance of 35-dBm output IP3, while maintaining less than 4-dB noise figure across the whole 1-dB bandwidth. The device is internally matched for 100-Ω differential input impedance providing easy interface with an RF-sampling or Zero-IF analog front-end (AFE) at the input. Also, the device is internally matched for 50-Ω single-ended output impedance required for easy interface with a post-amplifier, SAW filter, or PA. Operating on a single 3.3-V supply, the device consumes only 375 mW of active power making it suitable for high-density 5G massive MIMO applications. Also, the device is available in a space saving 2-mm × 2-mm, 12-pin QFN package. The device is rated for an operating temperature of up to 105°C to provide a robust system design. There is a 1.8-V JEDEC compliant power down pin available for fast power down and power up of the device suitable for time division duplex (TDD) systems. The LMH9126 is high-performance, single-channel, differential input to single-ended output transmit RF gain block amplifier supporting 2.6-GHz center frequency band. The device is well suited to support requirements for the next generation 5G AAS or small cell applications while driving the input of a power amplifier (PA). The RF amplifier provides 18-dB typical gain with good linearity performance of 35-dBm output IP3, while maintaining less than 4-dB noise figure across the whole 1-dB bandwidth. The device is internally matched for 100-Ω differential input impedance providing easy interface with an RF-sampling or Zero-IF analog front-end (AFE) at the input. Also, the device is internally matched for 50-Ω single-ended output impedance required for easy interface with a post-amplifier, SAW filter, or PA. Operating on a single 3.3-V supply, the device consumes only 375 mW of active power making it suitable for high-density 5G massive MIMO applications. Also, the device is available in a space saving 2-mm × 2-mm, 12-pin QFN package. The device is rated for an operating temperature of up to 105°C to provide a robust system design. There is a 1.8-V JEDEC compliant power down pin available for fast power down and power up of the device suitable for time division duplex (TDD) systems.

LMH9135 are high-performance, single-channel, differential input to single-ended output transmit radio frequency (RF) gain block amplifiers that support 3.2 – 4.2 GHz frequency band. The device can support the requirements for next generation 5G active antenna systems (AAS) or small-cell applications while driving the input of a power amplifier (PA). The RF amplifier provides 18 dB typical gain with good linearity performance of +31.5 dBm Output IP3, while maintaining less than 4 dB noise figure across the whole 1 dB bandwidth. The device is internally matched for 100-Ω differential input impedance providing easy interface with an RF-sampling or Zero-IF analog front-end (AFE) at the input. Also, the device is internally matched for 50-Ω single-ended output impedance that is required to easily interface with a post-amplifier, surface acoustic wave (SAW) filter, or power amplifier (PA). Operating on a single 3.3 V supply, the device consumes about 395 mW typical active power making it suitable for high-density 5G massive MIMO applications. Also, the device is available in a space saving 2 mm x 2 mm, 12-pin QFN package. The device is rated for an operating temperature of up to 105°C to provide a robust system design. There is a 1.8-V JEDEC compliant power down pin available for fast power down and power up of the device suitable for time division duplex (TDD) systems. LMH9135 are high-performance, single-channel, differential input to single-ended output transmit radio frequency (RF) gain block amplifiers that support 3.2 – 4.2 GHz frequency band. The device can support the requirements for next generation 5G active antenna systems (AAS) or small-cell applications while driving the input of a power amplifier (PA). The RF amplifier provides 18 dB typical gain with good linearity performance of +31.5 dBm Output IP3, while maintaining less than 4 dB noise figure across the whole 1 dB bandwidth. The device is internally matched for 100-Ω differential input impedance providing easy interface with an RF-sampling or Zero-IF analog front-end (AFE) at the input. Also, the device is internally matched for 50-Ω single-ended output impedance that is required to easily interface with a post-amplifier, surface acoustic wave (SAW) filter, or power amplifier (PA). Operating on a single 3.3 V supply, the device consumes about 395 mW typical active power making it suitable for high-density 5G massive MIMO applications. Also, the device is available in a space saving 2 mm x 2 mm, 12-pin QFN package. The device is rated for an operating temperature of up to 105°C to provide a robust system design. There is a 1.8-V JEDEC compliant power down pin available for fast power down and power up of the device suitable for time division duplex (TDD) systems.

The LMH9235 device is a high-performance, single-channel, single-ended input to differential output receive RF gain block amplifier supporting 3.6 GHz center frequency band. The device is well suited to support requirements for the next generation 5G AAS or small cell applications where LNA gain is not sufficient to drive full-scale of an analog front-end (AFE). The RF amplifier provides 17 dB typical gain with good linearity performance of 34 dBm Output IP3, while maintaining about 3 dB noise figure across the whole 1 dB bandwidth. The device is internally matched for 50 Ω impedance at both the single-ended input as well as the differential output providing easy interface with an RF-sampling or Zero-IF analog front-end (AFE). Operating on a single 3.3 V supply, the device consumes about 270 mW of active power making it suitable for high-density 5G massive MIMO applications. Also, the device is available in a space saving 2 mm x 2 mm, 12-pin QFN package. The device is rated for an operating temperature of up to 105°C to provide a robust system design. There is a 1.8 V JEDEC compliant power down pin available for fast power down and power up of the device suitable for time division duplex (TDD) systems. The LMH9235 device is a high-performance, single-channel, single-ended input to differential output receive RF gain block amplifier supporting 3.6 GHz center frequency band. The device is well suited to support requirements for the next generation 5G AAS or small cell applications where LNA gain is not sufficient to drive full-scale of an analog front-end (AFE). The RF amplifier provides 17 dB typical gain with good linearity performance of 34 dBm Output IP3, while maintaining about 3 dB noise figure across the whole 1 dB bandwidth. The device is internally matched for 50 Ω impedance at both the single-ended input as well as the differential output providing easy interface with an RF-sampling or Zero-IF analog front-end (AFE). Operating on a single 3.3 V supply, the device consumes about 270 mW of active power making it suitable for high-density 5G massive MIMO applications. Also, the device is available in a space saving 2 mm x 2 mm, 12-pin QFN package. The device is rated for an operating temperature of up to 105°C to provide a robust system design. There is a 1.8 V JEDEC compliant power down pin available for fast power down and power up of the device suitable for time division duplex (TDD) systems.

The LMK00101 is a high performance, low noise LVCMOS fanout buffer which can distribute 10 ultra-low jitter clocks from a differential, single ended, or crystal input. The LMK00101 supports synchronous output enable for glitch free operation. The ultra low-skew, low-jitter, and high PSRR make this buffer ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications. The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00101 can be easily configured through pin programming. The LMK00101 is a high performance, low noise LVCMOS fanout buffer which can distribute 10 ultra-low jitter clocks from a differential, single ended, or crystal input. The LMK00101 supports synchronous output enable for glitch free operation. The ultra low-skew, low-jitter, and high PSRR make this buffer ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications. The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00101 can be easily configured through pin programming.

The LMK00105 is a high-performance, low-noise LVCMOS fanout buffer which can distribute five ultra-low jitter clocks from a differential, single-ended, or crystal input. The LMK00105 supports synchronous output enable for glitch-free operation. The ultra low-skew, low-jitter, and high PSRR make this buffer ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications. The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00105 can be easily configured through pin programming. The LMK00105 is a high-performance, low-noise LVCMOS fanout buffer which can distribute five ultra-low jitter clocks from a differential, single-ended, or crystal input. The LMK00105 supports synchronous output enable for glitch-free operation. The ultra low-skew, low-jitter, and high PSRR make this buffer ideally suited for various networking, telecom, server and storage area networking, RRU LO reference distribution, medical and test equipment applications. The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00105 can be easily configured through pin programming.

The LMK00301 is a 3-GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock and data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of five differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00301 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies. The LMK00301 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system. The LMK00301 offers a design spin, the LMK00301A, that does not have power supply sequencing requirements between the core and output supply domains. The LMK00301 is a 3-GHz, 10-output differential fanout buffer intended for high-frequency, low-jitter clock and data distribution, and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of five differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00301 operates from a 3.3-V core supply and three independent 3.3-V or 2.5-V output supplies. The LMK00301 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system. The LMK00301 offers a design spin, the LMK00301A, that does not have power supply sequencing requirements between the core and output supply domains.

The LMK00304 is a 3-GHz 4-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 2 differential outputs and one LVCMOS output. The differential output banks can be mutually configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00304 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies. The LMK00304 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system. The LMK00304 is a 3-GHz 4-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 2 differential outputs and one LVCMOS output. The differential output banks can be mutually configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00304 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies. The LMK00304 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.