DS90UB9702-Q1FPD-Link IV quad deserializer hub with D-PHY CSI-2 output ports for 8MP+ cameras and other sensors | Unclassified | 2 | Active | The DS90UB9702-Q1 is an FPD-Link deserializer that delivers robust ultra-high-speed 7.55 Gbps forward channel and 47.1875 Mbps Bidirectional Control Channel for connecting up to four raw data sensors to central processing units over an automotive coaxial or STP cable. When coupled with DS90UB971-Q1 serializer, the deserializer receives video data from imagers supporting ultra-high resolutions (8MP+/40fps) or multiple sensors in various topologies.
Data is received and aggregated into two MIPI CSI-2 D-PHY outputs for interfacing with a downstream processor. An additional CSI port is used for port replication. The flexible MIPI CSI-2 outputs support multiple virtual channels interleaving per port to differentiate multiple sensors, exposures, and data types. This functionality features video aggregation and replication modes and supports input-to-output port as well as virtual channel (VC-ID) remapping.
Advanced data protection and diagnostic features support overall system functional safety. Multiple levels of data integrity checking and protection in conjunction with programmable health status interrupt helps ensure robust sensor module and link operation in vehicles.
The DS90UB9702-Q1 is an FPD-Link deserializer that delivers robust ultra-high-speed 7.55 Gbps forward channel and 47.1875 Mbps Bidirectional Control Channel for connecting up to four raw data sensors to central processing units over an automotive coaxial or STP cable. When coupled with DS90UB971-Q1 serializer, the deserializer receives video data from imagers supporting ultra-high resolutions (8MP+/40fps) or multiple sensors in various topologies.
Data is received and aggregated into two MIPI CSI-2 D-PHY outputs for interfacing with a downstream processor. An additional CSI port is used for port replication. The flexible MIPI CSI-2 outputs support multiple virtual channels interleaving per port to differentiate multiple sensors, exposures, and data types. This functionality features video aggregation and replication modes and supports input-to-output port as well as virtual channel (VC-ID) remapping.
Advanced data protection and diagnostic features support overall system functional safety. Multiple levels of data integrity checking and protection in conjunction with programmable health status interrupt helps ensure robust sensor module and link operation in vehicles. |
DS90UB971-Q1FPD-Link IV 7.55-Gbps serializer with CSI-2 interface for 8MP+ cameras, radar and other sensors | Interface | 2 | Active | The DS90UB971-Q1 serializer represents the first generation in FPD-Link IV serializers and is designed to support ultra-high-speed raw data sensors including 8MP+ Imagers, satellite RADAR, LIDAR, and Time-of-Flight (ToF) sensors. The chip delivers an 7.55Gbps forward channel and an ultra-low latency, 47.1875Mbps bidirectional control channel and supports power over a single coax (PoC) or STP cable. The DS90UB971-Q1 features advanced data protection and diagnostic features to support ADAS and automotive functional safety. Together with a companion deserializer, the DS90UB971-Q1 delivers precise multi-camera sensor clock and sensor synchronization.
The DS90UB971-Q1 is fully AEC-Q100 qualified with a wide temperature range of –40°C to 115°C. The serializer comes in a small 5mm × 5mm VQFN package for space-constrained sensor applications.
The DS90UB971-Q1 serializer represents the first generation in FPD-Link IV serializers and is designed to support ultra-high-speed raw data sensors including 8MP+ Imagers, satellite RADAR, LIDAR, and Time-of-Flight (ToF) sensors. The chip delivers an 7.55Gbps forward channel and an ultra-low latency, 47.1875Mbps bidirectional control channel and supports power over a single coax (PoC) or STP cable. The DS90UB971-Q1 features advanced data protection and diagnostic features to support ADAS and automotive functional safety. Together with a companion deserializer, the DS90UB971-Q1 delivers precise multi-camera sensor clock and sensor synchronization.
The DS90UB971-Q1 is fully AEC-Q100 qualified with a wide temperature range of –40°C to 115°C. The serializer comes in a small 5mm × 5mm VQFN package for space-constrained sensor applications. |
DS90UB9722-Q1Automotive FPD-Link IV dual deserializer hub with D-PHY CSI-2 output ports for 8MP+ cameras, sensors | Uncategorized | 2 | Active | The DS90UB9722-Q1 is an FPD-Link deserializer that delivers robust ultra-high-speed 7.55 Gbps forward channel and 47.1875 Mbps Bidirectional Control Channel for connecting up to two raw data sensors to central processing units over an automotive coaxial or STP cable. When coupled with DS90UB971-Q1 serializer, the deserializer receives video data from imagers supporting ultra-high resolutions (8MP+/40fps) or multiple sensors in various topologies.
Data is received and aggregated into two MIPI CSI-2 D-PHY outputs for interfacing with a downstream processor. The flexible MIPI CSI-2 outputs support multiple virtual channels interleaving per port to differentiate multiple sensors, exposures, and data types. This functionality features video aggregation and replication modes and supports input-to-output port as well as virtual channel (VC-ID) remapping.
Advanced data protection and diagnostic features support overall system functional safety. Multiple levels of data integrity checking and protection in conjunction with programmable health status interrupt helps ensure robust sensor module and link operation in vehicles.
The DS90UB9722-Q1 is an FPD-Link deserializer that delivers robust ultra-high-speed 7.55 Gbps forward channel and 47.1875 Mbps Bidirectional Control Channel for connecting up to two raw data sensors to central processing units over an automotive coaxial or STP cable. When coupled with DS90UB971-Q1 serializer, the deserializer receives video data from imagers supporting ultra-high resolutions (8MP+/40fps) or multiple sensors in various topologies.
Data is received and aggregated into two MIPI CSI-2 D-PHY outputs for interfacing with a downstream processor. The flexible MIPI CSI-2 outputs support multiple virtual channels interleaving per port to differentiate multiple sensors, exposures, and data types. This functionality features video aggregation and replication modes and supports input-to-output port as well as virtual channel (VC-ID) remapping.
Advanced data protection and diagnostic features support overall system functional safety. Multiple levels of data integrity checking and protection in conjunction with programmable health status interrupt helps ensure robust sensor module and link operation in vehicles. |
| Uncategorized | 1 | Active | DS90UB981-Q1 is a MIPI DSI to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UB981-Q1 is a D-PHY v1.2 compliant device that serializes a MIPI DSI input supporting video resolutions including 4K with 30-bit color depth. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C and GPIO data over a single channel or dual channels. Consolidation of video data and control over two FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the devices supports up to 720p and 1080p resolutions with 24-bit color depth over a single/dual link. In ADAS compatible mode, the device is interoperable with 936, 95x, 96x & 97x deserializers supporting resolutions up to 8MP+/40fps.
DS90UB981-Q1 is a MIPI DSI to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UB981-Q1 is a D-PHY v1.2 compliant device that serializes a MIPI DSI input supporting video resolutions including 4K with 30-bit color depth. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C and GPIO data over a single channel or dual channels. Consolidation of video data and control over two FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the devices supports up to 720p and 1080p resolutions with 24-bit color depth over a single/dual link. In ADAS compatible mode, the device is interoperable with 936, 95x, 96x & 97x deserializers supporting resolutions up to 8MP+/40fps. |
DS90UB983-Q14K DisplayPort™/eDP to FPD-Link IV bridge serializer | Unclassified | 1 | Active | The DS90UB983-Q1 is a DisplayPort/eDP to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UB983-Q1 is a VESA DP Standard v1.4 compatible device that supports advanced features such as MST, HBR3, and SuperFrame formats. The device is capable of supporting video resolution up to 4K resolutions with 30-bit color. 8b10b encoded DP data is serialized onto an FPD-Link IV interface output. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over a single channel or dual channels. Consolidation of video data and control over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the device supports up to 720p and 1080p resolutions with 24 bit color depth over a single/dual link.
The DS90UB983-Q1 is a DisplayPort/eDP to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UB983-Q1 is a VESA DP Standard v1.4 compatible device that supports advanced features such as MST, HBR3, and SuperFrame formats. The device is capable of supporting video resolution up to 4K resolutions with 30-bit color. 8b10b encoded DP data is serialized onto an FPD-Link IV interface output. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over a single channel or dual channels. Consolidation of video data and control over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the device supports up to 720p and 1080p resolutions with 24 bit color depth over a single/dual link. |
DS90UB984-Q14K FPD-Link IV to embedded DisplayPort™ bridge deserializer | Interface | 1 | Active | The DS90UB984-Q1 is an FPD-Link IV to DisplayPort (DP) / Embedded DisplayPort (eDP) bridge device. In conjunction with an FPD-Link IV serializer, the chipset receives a high-speed serialized interface over low-cost 50Ω coax or STP/STQ cables. The DS90UB984-Q1 is a VESA DP v1.4a/eDP v1.4b compatible device that supports advanced features such as HBR3, and SuperFrame formats. The device supports video resolutions of 4K 30-bit color and higher. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over the same link. Consolidation of video data and control over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible FPD-Link III mode, the device supports up to 2K resolutions with 24-bit color depth over a single/dual link .
The DS90UB984-Q1 is an FPD-Link IV to DisplayPort (DP) / Embedded DisplayPort (eDP) bridge device. In conjunction with an FPD-Link IV serializer, the chipset receives a high-speed serialized interface over low-cost 50Ω coax or STP/STQ cables. The DS90UB984-Q1 is a VESA DP v1.4a/eDP v1.4b compatible device that supports advanced features such as HBR3, and SuperFrame formats. The device supports video resolutions of 4K 30-bit color and higher. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over the same link. Consolidation of video data and control over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible FPD-Link III mode, the device supports up to 2K resolutions with 24-bit color depth over a single/dual link . |
| Interface | 1 | Active | The DS90UB988-Q1 is an FPD-Link IV to OpenLDI bridge device. In conjunction with an FPD-Link IV serializer, the chipset receives a high-speed serialized interface over low-cost 50Ω coax or STP/STQ cables. The DS90UB988-Q1 supports OpenLDI (10 LVDS data lanes + 2 clocks) interface with video up to 420MHz PCLK. This provides a bridge between sources such as GPUs to connect to existing LVDS based displays or application processors.
The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over the same link. Consolidation of video and control data over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible FPD-Link III mode, the device supports up to 2K resolutions with 24-bit color depth over a single/dual link .
The DS90UB988-Q1 is an FPD-Link IV to OpenLDI bridge device. In conjunction with an FPD-Link IV serializer, the chipset receives a high-speed serialized interface over low-cost 50Ω coax or STP/STQ cables. The DS90UB988-Q1 supports OpenLDI (10 LVDS data lanes + 2 clocks) interface with video up to 420MHz PCLK. This provides a bridge between sources such as GPUs to connect to existing LVDS based displays or application processors.
The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over the same link. Consolidation of video and control data over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible FPD-Link III mode, the device supports up to 2K resolutions with 24-bit color depth over a single/dual link . |
DS90UH925AQ-Q15 to 85 MHz 24-bit Color FPD-Link III Serializer with HDCP | Integrated Circuits (ICs) | 3 | Unknown | The DS90UH925AQ serializer, in conjunction with the DS90UH926Q deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UH925AQ serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.
EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.
Remote interrupts from the downstream DS90UH926Q deserializer are mirrored to a local output pin.
The DS90UH925AQ serializer, in conjunction with the DS90UH926Q deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UH925AQ serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.
EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.
Remote interrupts from the downstream DS90UH926Q deserializer are mirrored to a local output pin. |
| Serializers, Deserializers | 3 | Unknown | |
DS90UH928Q-Q15MHz - 85MHz 24-bit Color FPD-Link III to FPD-Link Deserializer with HDCP | Serializers, Deserializers | 2 | Unknown | The DS90UH928Q-Q1 deserializer, in conjunction with a DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI (FPD-Link)), and I2S audio data. The digital video and audio data is protected using the industry standard HDCP copy protection scheme.The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.
The DS90UH928Q-Q1 deserializer, in conjunction with a DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI (FPD-Link)), and I2S audio data. The digital video and audio data is protected using the industry standard HDCP copy protection scheme.The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory. |
