DS90UH925AQ-Q1 Series
5 to 85 MHz 24-bit Color FPD-Link III Serializer with HDCP
Manufacturer: Texas Instruments
Catalog
5 to 85 MHz 24-bit Color FPD-Link III Serializer with HDCP
Key Features
• Integrated HDCP Cipher Engine with On-chip Key StorageBidirectional Control Interface Channel Interface with I2CCompatible Serial Control BusSupports High Definition (720p) Digital Video FormatRGB888 + VS, HS, DE and I2S Audio Supported5 – 85 MHz PCLK SupportedSingle 3.3 V Operation with 1.8 V or 3.3 V CompatibleLVCMOS I/O InterfaceAC-coupled STP Interconnect up to 10 metersParallel LVCMOS Video InputsDC-balanced & Scrambled Data with Embedded ClockSupports HDCP Repeater ApplicationDedicated Interrupt Pin for Remote InterruptsInternal Pattern GenerationLow Power Modes Minimize Power DissipationAutomotive Grade Product: AEC-Q100 Grade 2 Qualified>8 kV HBM and ISO 10605 ESD ratingBackward Compatible ModesIntegrated HDCP Cipher Engine with On-chip Key StorageBidirectional Control Interface Channel Interface with I2CCompatible Serial Control BusSupports High Definition (720p) Digital Video FormatRGB888 + VS, HS, DE and I2S Audio Supported5 – 85 MHz PCLK SupportedSingle 3.3 V Operation with 1.8 V or 3.3 V CompatibleLVCMOS I/O InterfaceAC-coupled STP Interconnect up to 10 metersParallel LVCMOS Video InputsDC-balanced & Scrambled Data with Embedded ClockSupports HDCP Repeater ApplicationDedicated Interrupt Pin for Remote InterruptsInternal Pattern GenerationLow Power Modes Minimize Power DissipationAutomotive Grade Product: AEC-Q100 Grade 2 Qualified>8 kV HBM and ISO 10605 ESD ratingBackward Compatible Modes
Description
AI
The DS90UH925AQ serializer, in conjunction with the DS90UH926Q deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UH925AQ serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.
EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.
Remote interrupts from the downstream DS90UH926Q deserializer are mirrored to a local output pin.
The DS90UH925AQ serializer, in conjunction with the DS90UH926Q deserializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB Video Interface into a single pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports video and audio data transmission and full duplex control including I2C communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UH925AQ serializer embeds the clock, content protects the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 RGB data bits are serialized along with three video control signals and up to two I2S data inputs.
EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.
The HDCP cipher engine is implemented in the serializer and deserializer. HDCP keys are stored in on-chip memory.
Remote interrupts from the downstream DS90UH926Q deserializer are mirrored to a local output pin.
