Catalog
4K FPD-Link IV to OpenLDI deserializer
Key Features
• OpenLDI (OLDI) transmitter2 Port OLDI output (Dual Pixel Link) up to 420MHz OLDI clockEach Port supports 8MHz to 210MHz OLDI clockConfigurable 18-bit, 24-bit, 30-bit RGBStream synchronization and splittingFPD-Link IV interfaceUp to 13.5/12.528/10.8/6.75/3.375Gbps per channel; Up to 27Gbps over dual channelsCoax/STP interconnect supportSelectable 1, 2 channelsDaisy-chain and splittingAdaptive equalizationOptional digital RGB parallel output interface supports 8MHz to 125MHz PCLKUltra-low latency control channelTwo fast-mode plus I2C up to 1MHz (up to 3.4MHz for local bus access)High-speed GPIOsSupports SPI and UART pass-through GPIOsBackwards compatibility720p 92x and 1080p/2K 94x FPD-Link III product familiesSecurity and diagnosticsLink diagnosticsVoltage and temperature monitoringBIST and pattern generationCRC and error diagnosticsECC on control bitsUnique ID for counterfeit protectionAdvanced link robustness and EMC controlSpread Spectrum Clocking Generation (SSCG)Adaptive Receiver Equalization (AEQ)Low power operation1.8V and 1.15V dual power supplyAEC-Q100 qualified for automotive applicationsAEC-Q Grade-Level 2 , –40°C to 105°CISO 10605 and IEC 61000-4-2 ESD compliantOpenLDI (OLDI) transmitter2 Port OLDI output (Dual Pixel Link) up to 420MHz OLDI clockEach Port supports 8MHz to 210MHz OLDI clockConfigurable 18-bit, 24-bit, 30-bit RGBStream synchronization and splittingFPD-Link IV interfaceUp to 13.5/12.528/10.8/6.75/3.375Gbps per channel; Up to 27Gbps over dual channelsCoax/STP interconnect supportSelectable 1, 2 channelsDaisy-chain and splittingAdaptive equalizationOptional digital RGB parallel output interface supports 8MHz to 125MHz PCLKUltra-low latency control channelTwo fast-mode plus I2C up to 1MHz (up to 3.4MHz for local bus access)High-speed GPIOsSupports SPI and UART pass-through GPIOsBackwards compatibility720p 92x and 1080p/2K 94x FPD-Link III product familiesSecurity and diagnosticsLink diagnosticsVoltage and temperature monitoringBIST and pattern generationCRC and error diagnosticsECC on control bitsUnique ID for counterfeit protectionAdvanced link robustness and EMC controlSpread Spectrum Clocking Generation (SSCG)Adaptive Receiver Equalization (AEQ)Low power operation1.8V and 1.15V dual power supplyAEC-Q100 qualified for automotive applicationsAEC-Q Grade-Level 2 , –40°C to 105°CISO 10605 and IEC 61000-4-2 ESD compliant
Description
AI
The DS90UB988-Q1 is an FPD-Link IV to OpenLDI bridge device. In conjunction with an FPD-Link IV serializer, the chipset receives a high-speed serialized interface over low-cost 50Ω coax or STP/STQ cables. The DS90UB988-Q1 supports OpenLDI (10 LVDS data lanes + 2 clocks) interface with video up to 420MHz PCLK. This provides a bridge between sources such as GPUs to connect to existing LVDS based displays or application processors.
The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over the same link. Consolidation of video and control data over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible FPD-Link III mode, the device supports up to 2K resolutions with 24-bit color depth over a single/dual link .
The DS90UB988-Q1 is an FPD-Link IV to OpenLDI bridge device. In conjunction with an FPD-Link IV serializer, the chipset receives a high-speed serialized interface over low-cost 50Ω coax or STP/STQ cables. The DS90UB988-Q1 supports OpenLDI (10 LVDS data lanes + 2 clocks) interface with video up to 420MHz PCLK. This provides a bridge between sources such as GPUs to connect to existing LVDS based displays or application processors.
The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over the same link. Consolidation of video and control data over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible FPD-Link III mode, the device supports up to 2K resolutions with 24-bit color depth over a single/dual link .