DS90UB924-Q15 MHz to 96 MHz 24-bit Color FPD-Link III to OpenLDI Deserializer | Interface | 2 | Active | The DS90UB924-Q1 deserializer, in conjunction with a DS90UB921-Q1, DS90UB925Q-Q1, DS90UB927Q-Q1, DS90UB929-Q1, DS90UB949-Q1, or DS90UB947-Q1 serializer, provides a solution for distribution of digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI), and I2S audio data. The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling.
The DS90UB924-Q1 deserializer, in conjunction with a DS90UB921-Q1, DS90UB925Q-Q1, DS90UB927Q-Q1, DS90UB929-Q1, DS90UB949-Q1, or DS90UB947-Q1 serializer, provides a solution for distribution of digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI), and I2S audio data. The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling. |
DS90UB925Q-Q15 - 85 MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel | Evaluation and Demonstration Boards and Kits | 3 | Active | The DS90UB925Q-Q1 serializer, in conjunction with the DS90UB926Q-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications.
The chipset is ideally suited for automotive video-display systems with HD formats and automotive vision systems with megapixel resolutions. The DS90UB925Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This chipset translates a parallel interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed video data transmission and bidirectional control communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB925Q-Q1 serializer embeds the clock, DC scrambles & balances the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 data bits are serialized along the video control signals.
Serial transmission is optimized by a user selectable de-emphasis. EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility.
The DS90UB925Q-Q1 serializer, in conjunction with the DS90UB926Q-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications.
The chipset is ideally suited for automotive video-display systems with HD formats and automotive vision systems with megapixel resolutions. The DS90UB925Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This chipset translates a parallel interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed video data transmission and bidirectional control communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB925Q-Q1 serializer embeds the clock, DC scrambles & balances the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 data bits are serialized along the video control signals.
Serial transmission is optimized by a user selectable de-emphasis. EMI is minimized by the use of low voltage differential signaling, data scrambling and randomization and spread spectrum clocking compatibility. |
DS90UB926Q-Q15-85 MHz 24-bit Color FPD-Link III Deserializer with Bidirectional Control Channel | Evaluation Boards | 4 | Active | The DS90UB926Q-Q1 deserializer, in conjunction with the DS90UB925Q-Q1 serializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image-sensing applications.
This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB926Q-Q1 deserializer recovers the RGB data, three video control signals, and four synchronized I2S audio signals. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock.
The DS90UB926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data.
An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features.
The DS90UB926Q-Q1 deserializer, in conjunction with the DS90UB925Q-Q1 serializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image-sensing applications.
This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB926Q-Q1 deserializer recovers the RGB data, three video control signals, and four synchronized I2S audio signals. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock.
The DS90UB926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data.
An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features. |
DS90UB927Q-Q15MHz - 85MHz 24-bit Color FPD-Link III Serializer with Bidirectional Control Channel | Interface | 1 | Active | The DS90UB927Q-Q1 serializer, in conjunction with a DS90UB928Q-Q1 or DS90UB926Q-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications.
The chipset is ideally suited for automotive video display systens with HD formats and automotive vision systems with megapixel resolutions. The DS90UB927Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This device translates a FPD-Link video interface into a single-pair high-speed serialized interface. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB927Q-Q1 serializer embeds the clock and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I2S data inputs.
The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and DC-balancing.
The DS90UB927Q-Q1 serializer, in conjunction with a DS90UB928Q-Q1 or DS90UB926Q-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications.
The chipset is ideally suited for automotive video display systens with HD formats and automotive vision systems with megapixel resolutions. The DS90UB927Q-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This device translates a FPD-Link video interface into a single-pair high-speed serialized interface. The FPD-Link III serial bus scheme supports full duplex, high speed forward channel data transmission and low-speed back channel communication over a single differential link. Consolidation of audio, video, and control data over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
The DS90UB927Q-Q1 serializer embeds the clock and level shifts the signals to high-speed differential signaling. Up to 24 RGB data bits are serialized along with three video control signals, and up to four I2S data inputs.
The FPD-Link data interface allows for easy interfacing with data sources while also minimizing EMI and bus width. EMI on the high-speed FPD-Link III bus is minimized using low voltage differential signaling, data scrambling and randomization, and DC-balancing. |
DS90UB928Q-Q1FPD-Link III Deserializer with Bidirectional Control Channel | Development Boards, Kits, Programmers | 2 | Active | The DS90UB928Q-Q1 deserializer, in conjunction with a DS90UB925Q-Q1 or DS90UB927Q-Q1 serializer, provides a solution for distribution of digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI (FPD-Link)), and I2S audio data. The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling.
The DS90UB928Q-Q1 deserializer, in conjunction with a DS90UB925Q-Q1 or DS90UB927Q-Q1 serializer, provides a solution for distribution of digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI (FPD-Link)), and I2S audio data. The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling. |
| Evaluation Boards | 2 | Active | The DS90UB929-Q1 is an HDMI to FPD-Link III bridge device which, in conjunction with the FPD-Link III DS90UB926Q-Q1/DS90UB928Q-Q1 deserializers, supplies 1-lane high-speed serial stream over cost-effective 50-Ω single-ended coaxial or 100-Ω differential shielded twisted-pair (STP) cable. It serializes an HDMI v1.4b input supporting video resolutions up to WXGA and 720p with 24-bit color depth. The DS90UB929-Q1 is also compatible with the DS90UB940-Q1/DS90UB948-Q1 deserializers.
The FPD-Link III interface supports video and audio data transmission and full duplex control, including I2C communication, over the same differential link. The consolidation of video data and control over one differential pair can reduce the interconnect size and weight and can simplify system design. EMI is minimized by the use of low-voltage differential signaling, data scrambling, and randomization.
The DS90UB929-Q1 supports multi-channel audio received through HDMI or an external I2S interface. The device also supplies an optional auxiliary audio interface.
The DS90UB929-Q1 is an HDMI to FPD-Link III bridge device which, in conjunction with the FPD-Link III DS90UB926Q-Q1/DS90UB928Q-Q1 deserializers, supplies 1-lane high-speed serial stream over cost-effective 50-Ω single-ended coaxial or 100-Ω differential shielded twisted-pair (STP) cable. It serializes an HDMI v1.4b input supporting video resolutions up to WXGA and 720p with 24-bit color depth. The DS90UB929-Q1 is also compatible with the DS90UB940-Q1/DS90UB948-Q1 deserializers.
The FPD-Link III interface supports video and audio data transmission and full duplex control, including I2C communication, over the same differential link. The consolidation of video data and control over one differential pair can reduce the interconnect size and weight and can simplify system design. EMI is minimized by the use of low-voltage differential signaling, data scrambling, and randomization.
The DS90UB929-Q1 supports multi-channel audio received through HDMI or an external I2S interface. The device also supplies an optional auxiliary audio interface. |
DS90UB933-Q112-bit 100 MHz FPD-Link III Serializer for 1MP/60fps and 2MP/30fps Cameras | Integrated Circuits (ICs) | 1 | Active | The DS90UB933-Q1 device offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single coaxial cable or differential pair. The DS90UB933-Q1 device incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer/deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus.
Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical-bidirectional control channel information. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.
The DS90UB933-Q1 device offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single coaxial cable or differential pair. The DS90UB933-Q1 device incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer/deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus.
Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical-bidirectional control channel information. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects. |
DS90UB934-Q112-bit 100 MHz FPD-Link III Deserializer for 1MP/60fps and 2MP/30fps Cameras | Evaluation Boards | 3 | Active | The DS90UB934-Q1 FPD-Link III deserializer, in conjunction with the DS90UB913A/933-Q1 serializers, supports the video transport needs with an ultra-high-speed forward channel and an embedded bidirectional control channel. The DS90UB934-Q1 converts the FPD-Link III stream into a parallel CMOS output interface designed to support automotive image sensors up to 12 bits at 100 MHz with resolutions including 1MP/60fps and 2MP/30fps.
The DS90UB933/934 chipset is fully AEC-Q100 qualified and designed to receive data across either 50-Ω single-ended coaxial or 100-Ω shielded-twisted pair (STP) cable assemblies. The DS90UB934-Q1 uses an advanced adaptive equalizer to allow support of various cable lengths and types with no additional programming required.
The DS90UB934-Q1 is improved over prior generations of ADAS FPD-Link III deserializer devices (such as DS90UB914A-Q1) offering higher bandwidth support with additional enhancements.
The DS90UB934-Q1 FPD-Link III deserializer, in conjunction with the DS90UB913A/933-Q1 serializers, supports the video transport needs with an ultra-high-speed forward channel and an embedded bidirectional control channel. The DS90UB934-Q1 converts the FPD-Link III stream into a parallel CMOS output interface designed to support automotive image sensors up to 12 bits at 100 MHz with resolutions including 1MP/60fps and 2MP/30fps.
The DS90UB933/934 chipset is fully AEC-Q100 qualified and designed to receive data across either 50-Ω single-ended coaxial or 100-Ω shielded-twisted pair (STP) cable assemblies. The DS90UB934-Q1 uses an advanced adaptive equalizer to allow support of various cable lengths and types with no additional programming required.
The DS90UB934-Q1 is improved over prior generations of ADAS FPD-Link III deserializer devices (such as DS90UB914A-Q1) offering higher bandwidth support with additional enhancements. |
DS90UB935-Q1FPD-Link III 3-Gbps serializer with CSI-2 interface for 1 MP & 60 fps | Interface | 1 | Active | The DS90UB935-Q1 serializer is part of TI’s FPD-Link III device family designed to support high-speed raw data sensors including cameras, satellite RADAR, LIDAR, and Time-of-Flight (ToF) sensors. The chip delivers a high-speed forward channel and an ultra-low latency, bidirectional control channel and supports power over a single coax (PoC) or STP cable. The DS90UB935-Q1 features advanced data protection and diagnostic features to support ADAS and autonomous driving. Together with a companion deserializer, the DS90UB935-Q1 delivers precise multi-camera sensor clock and sensor synchronization.
The DS90UB935-Q1 is fully AEC-Q100 qualified with a -40°C to 105°C wide temperature range. The serializer comes in a small 5mm × 5mm VQFN package for space-constrained sensor applications.
The DS90UB935-Q1 serializer is part of TI’s FPD-Link III device family designed to support high-speed raw data sensors including cameras, satellite RADAR, LIDAR, and Time-of-Flight (ToF) sensors. The chip delivers a high-speed forward channel and an ultra-low latency, bidirectional control channel and supports power over a single coax (PoC) or STP cable. The DS90UB935-Q1 features advanced data protection and diagnostic features to support ADAS and autonomous driving. Together with a companion deserializer, the DS90UB935-Q1 delivers precise multi-camera sensor clock and sensor synchronization.
The DS90UB935-Q1 is fully AEC-Q100 qualified with a -40°C to 105°C wide temperature range. The serializer comes in a small 5mm × 5mm VQFN package for space-constrained sensor applications. |
DS90UB936-Q11MP MIPI CSI-2 FPD-Link III Deserializer for 1MP/60fps & 2MP/30 fps | Serializers, Deserializers | 2 | Active | The DS90UB936-Q1 is a versatile deserializer capable of receiving serialized sensor data from source through an FPD-Link III interface. When paired with a DS90UB935-Q1 serializer, the DS90UB936-Q1 receives data from imagers supporting up to 2.528 Gbps CSI-2 throughput. The DS90UB936-Q1 may also be used with other compatible serializers such as the DS90UB933-Q1, and DS90UB913A-Q1. When configuring the CSI-2 interface for 2-lane operation, a duplicate MIPI CSI-2 clock lane is available to provide a replicated output. Replication mode creates two copies of the video stream for data logging and parallel processing.
The DS90UB935/936-Q1 chipset is AEC-Q100 qualified and designed to receive data across either 50-Ω single-ended coaxial or 100-Ω differential STP cables. AEC-Q100 qualification includes device temperature grade 2 (–40℃ to +105℃ ambient operating temperature range), device HBM ESD classification level ±4.5 kV, and device CDM ESD classification level C5. The deserializer hub is ideal for Power-over-Coax applications and the receive equalizer automatically adapts to compensate for cable loss characteristics with no additional programming required, including cable degradation over time.
Each FPD-Link III interface includes a separate low latency bidirectional control channel (BCC) that continuously conveys I2C, GPIO, and other control information. GPIO signals purposed for sensor synchronization and diagnostic features also make use of the BCC.
The DS90UB936-Q1 is a versatile deserializer capable of receiving serialized sensor data from source through an FPD-Link III interface. When paired with a DS90UB935-Q1 serializer, the DS90UB936-Q1 receives data from imagers supporting up to 2.528 Gbps CSI-2 throughput. The DS90UB936-Q1 may also be used with other compatible serializers such as the DS90UB933-Q1, and DS90UB913A-Q1. When configuring the CSI-2 interface for 2-lane operation, a duplicate MIPI CSI-2 clock lane is available to provide a replicated output. Replication mode creates two copies of the video stream for data logging and parallel processing.
The DS90UB935/936-Q1 chipset is AEC-Q100 qualified and designed to receive data across either 50-Ω single-ended coaxial or 100-Ω differential STP cables. AEC-Q100 qualification includes device temperature grade 2 (–40℃ to +105℃ ambient operating temperature range), device HBM ESD classification level ±4.5 kV, and device CDM ESD classification level C5. The deserializer hub is ideal for Power-over-Coax applications and the receive equalizer automatically adapts to compensate for cable loss characteristics with no additional programming required, including cable degradation over time.
Each FPD-Link III interface includes a separate low latency bidirectional control channel (BCC) that continuously conveys I2C, GPIO, and other control information. GPIO signals purposed for sensor synchronization and diagnostic features also make use of the BCC. |
