DS90UH941AS-Q12K DSI to FPD-Link III bridge serializer with video splitting and HDCP | Interface | 19 | Unknown | The DS90UH949A-Q1 is a HDMI-to-FPD-Link III bridge device which, paired with the FPD-Link III DS90UH940A-Q1/DS90UH948A-Q1 deserializers, supplies 1-lane or 2-lane high-speed serial streams over cost-effective 50-Ω single-ended coaxial, or 100-Ω differential shielded twisted-pair (STP) and shielded twisted quad (STQ) cables. The device can serialize a HDMI v1.4b input to support video resolutions up to 2K with 24-bit color depth.
The FPD-Link III interface supports video and audio data transmission and full duplex control, including I2C and SPI communication, over the same differential link. Consolidation of video data and control over two differential pairs can decrease the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward-compatible mode, the device supports up to 1080p for 94x deserializers and 720p for 92x deserializers with 24-bit color depth over a single differential link.
The DS90UH949A-Q1 supports HDCP Repeater applications where all authentication and encryption functions are handled without the need for an external controller. HDMI audio and video data are decrypted at the input and re-encrypted before the data is sent to the FPD-Link III interface.
The DS90UH949A-Q1 supports multi-channel audio received through HDMI or an external I2S interface. The device also has an optional auxiliary audio interface.
The DS90UH949A-Q1 is a HDMI-to-FPD-Link III bridge device which, paired with the FPD-Link III DS90UH940A-Q1/DS90UH948A-Q1 deserializers, supplies 1-lane or 2-lane high-speed serial streams over cost-effective 50-Ω single-ended coaxial, or 100-Ω differential shielded twisted-pair (STP) and shielded twisted quad (STQ) cables. The device can serialize a HDMI v1.4b input to support video resolutions up to 2K with 24-bit color depth.
The FPD-Link III interface supports video and audio data transmission and full duplex control, including I2C and SPI communication, over the same differential link. Consolidation of video data and control over two differential pairs can decrease the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward-compatible mode, the device supports up to 1080p for 94x deserializers and 720p for 92x deserializers with 24-bit color depth over a single differential link.
The DS90UH949A-Q1 supports HDCP Repeater applications where all authentication and encryption functions are handled without the need for an external controller. HDMI audio and video data are decrypted at the input and re-encrypted before the data is sent to the FPD-Link III interface.
The DS90UH949A-Q1 supports multi-channel audio received through HDMI or an external I2S interface. The device also has an optional auxiliary audio interface. |
| Integrated Circuits (ICs) | 1 | Active | |
DS90UH981-Q14K DSI to FPD-Link IV bridge serializer with HDCP | Unclassified | 2 | Active | DS90UH981-Q1 is a MIPI DSI to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UH981-Q1 is a D-PHY v1.2 compliant device that serializes a MIPI DSI input supporting video resolutions including 4K with 30-bit color depth. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C and GPIO data over a single channel or dual channels. Consolidation of video data and control over two FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the devices supports up to 720p and 1080p resolutions with 24-bit color depth over a single/dual link as well as HDCP v1.4 support when paired with an HDCP-capable deserializer. In ADAS compatible mode, the device is interoperable with 936, 95x, 96x & 97x deserializers supporting resolutions up to 8MP+/40fps.
DS90UH981-Q1 is a MIPI DSI to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UH981-Q1 is a D-PHY v1.2 compliant device that serializes a MIPI DSI input supporting video resolutions including 4K with 30-bit color depth. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C and GPIO data over a single channel or dual channels. Consolidation of video data and control over two FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the devices supports up to 720p and 1080p resolutions with 24-bit color depth over a single/dual link as well as HDCP v1.4 support when paired with an HDCP-capable deserializer. In ADAS compatible mode, the device is interoperable with 936, 95x, 96x & 97x deserializers supporting resolutions up to 8MP+/40fps. |
DS90UH983-Q14K DisplayPort™/eDP to FPD-Link IV bridge serializer with HDCP | Unclassified | 1 | Active | The DS90UH983-Q1 is a DisplayPort/eDP to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UH983-Q1 is a VESA DP Standard v1.4 compatible device that supports advanced features such as MST, HBR3, and SuperFrame formats. The device is capable of supporting video resolution up to 4K resolutions with 30-bit color. 8b10b encoded DP data is serialized onto an FPD-Link IV interface output. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over a single channel or dual channels. Consolidation of video data and control over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the device supports up to 720p and 1080p resolutions with 24 bit color depth over a single/dual link as well as HDCP v1.4 support when paired with an HDCP-capable deserializer.
The DS90UH983-Q1 is a DisplayPort/eDP to FPD-Link III/IV bridge device. In conjunction with an FPD-Link IV deserializer, the chipset provides a high-speed serialized interface over low-cost 50Ω coax or STP cables. The DS90UH983-Q1 is a VESA DP Standard v1.4 compatible device that supports advanced features such as MST, HBR3, and SuperFrame formats. The device is capable of supporting video resolution up to 4K resolutions with 30-bit color. 8b10b encoded DP data is serialized onto an FPD-Link IV interface output. The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over a single channel or dual channels. Consolidation of video data and control over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, SSCG, and randomization. In backward compatible mode, the device supports up to 720p and 1080p resolutions with 24 bit color depth over a single/dual link as well as HDCP v1.4 support when paired with an HDCP-capable deserializer. |
DS90UH988-Q14K FPD-Link IV to OpenLDI deserializer with HDCP | Uncategorized | 1 | Active | The DS90UH988-Q1 is an FPD-Link IV to OpenLDI bridge device. In conjunction with an FPD-Link IV serializer, the chipset receives a high-speed serialized interface over low-cost 50Ω coax or STP/STQ cables. The DS90UH988-Q1 supports OpenLDI (10 LVDS data lanes + 2 clocks) interface with video up to 420MHz PCLK. This provides a bridge between sources such as GPUs to connect to existing LVDS based displays or application processors.
The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over the same link. Consolidation of video and control data over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible FPD-Link III mode, the device supports up to 2K resolutions with 24-bit color depth over a single/dual link as well as HDCP v1.4 support when paired with an HDCP capable serializer.
The DS90UH988-Q1 is an FPD-Link IV to OpenLDI bridge device. In conjunction with an FPD-Link IV serializer, the chipset receives a high-speed serialized interface over low-cost 50Ω coax or STP/STQ cables. The DS90UH988-Q1 supports OpenLDI (10 LVDS data lanes + 2 clocks) interface with video up to 420MHz PCLK. This provides a bridge between sources such as GPUs to connect to existing LVDS based displays or application processors.
The FPD-Link IV interface supports video and audio data transmission and full duplex control, including I2C, and GPIO data over the same link. Consolidation of video and control data over FPD-Link IV lanes reduces the interconnect size and weight and simplifies system design. EMI is minimized by the use of low voltage differential signaling, data scrambling, and randomization. In backward compatible FPD-Link III mode, the device supports up to 2K resolutions with 24-bit color depth over a single/dual link as well as HDCP v1.4 support when paired with an HDCP capable serializer. |
DS90UR124-Q15-43MHz DC-Balanced 24-Bit FPD-Link II Deserializer - Automotive Grade | Serializers, Deserializers | 3 | Active | The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK. |
DS90UR241-Q15-43MHz DC-Balanced 24-Bit FPD-Link II Serializer - Automotive Grade | Interface | 1 | Active | The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK. |
| Interface | 1 | Active | The DS90UR903Q/DS90UR904Q chipset offers a FPD-Link II interface with a high-speed forward channel for data transmission over a single differential pair. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE). The serializer converts 21 bit data over a single high-speed serial stream. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The Serializer is offered in a 40-pin WQFN package and the Deserializer is offered in a 48-pin WQFN package.
The DS90UR903Q/DS90UR904Q chipset offers a FPD-Link II interface with a high-speed forward channel for data transmission over a single differential pair. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE). The serializer converts 21 bit data over a single high-speed serial stream. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The Serializer is offered in a 40-pin WQFN package and the Deserializer is offered in a 48-pin WQFN package. |
| Interface | 2 | Active | The DS90UR903Q/DS90UR904Q chipset offers a FPD-Link II interface with a high-speed forward channel for data transmission over a single differential pair. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE). The serializer converts 21 bit data over a single high-speed serial stream. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The Serializer is offered in a 40-pin WQFN package and the Deserializer is offered in a 48-pin WQFN package.
The DS90UR903Q/DS90UR904Q chipset offers a FPD-Link II interface with a high-speed forward channel for data transmission over a single differential pair. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE). The serializer converts 21 bit data over a single high-speed serial stream. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
The Serializer is offered in a 40-pin WQFN package and the Deserializer is offered in a 48-pin WQFN package. |
| Integrated Circuits (ICs) | 1 | Active | The DS90UR90xQ-Q1 chipset translates a parallel RGB video interface into a high-speed serialized interface over a single pair. This serial bus scheme makes system design easy by eliminating skew problems between clock and data, reducing the number of connector pins, reducing the interconnect size, weight, cost, and easing overall PCB layout. In addition, internal DC-balanced decoding is used to support AC-coupled interconnects.
The DS90UR905Q-Q1 serializer embeds the clock, balances the data payload, and level shifts the signals to high-speed, low voltage differential signaling. Up to 24 inputs are serialized, along with the three video control signals. This supports full24-bit color or 18-bit color and 6 general-purpose signals (for example, Audio I2S applications).
The DS90UR906Q-Q1 deserializer recovers the data (RGB) and control signals and extracts the clock from the serial stream. The DS90UR906Q-Q1 is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.
Serial transmission is optimized by a user-selectable de-emphasis, differential output level select features, and receiver equalization. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking compatibility. The deserializer may be configured to generate spread spectrum clock and data on its parallel outputs.
The DS90UR905Q-Q1 serializer is offered in a 48-pin WQFN and the DS90UR906Q-Q1 (deserializer) is offered in a 60-pin WQFN package. They are specified over the automotive AEC-Q100 grade 2 temperature range of –40°C to +105°C.
The DS90UR90xQ-Q1 chipset translates a parallel RGB video interface into a high-speed serialized interface over a single pair. This serial bus scheme makes system design easy by eliminating skew problems between clock and data, reducing the number of connector pins, reducing the interconnect size, weight, cost, and easing overall PCB layout. In addition, internal DC-balanced decoding is used to support AC-coupled interconnects.
The DS90UR905Q-Q1 serializer embeds the clock, balances the data payload, and level shifts the signals to high-speed, low voltage differential signaling. Up to 24 inputs are serialized, along with the three video control signals. This supports full24-bit color or 18-bit color and 6 general-purpose signals (for example, Audio I2S applications).
The DS90UR906Q-Q1 deserializer recovers the data (RGB) and control signals and extracts the clock from the serial stream. The DS90UR906Q-Q1 is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided.
Serial transmission is optimized by a user-selectable de-emphasis, differential output level select features, and receiver equalization. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking compatibility. The deserializer may be configured to generate spread spectrum clock and data on its parallel outputs.
The DS90UR905Q-Q1 serializer is offered in a 48-pin WQFN and the DS90UR906Q-Q1 (deserializer) is offered in a 60-pin WQFN package. They are specified over the automotive AEC-Q100 grade 2 temperature range of –40°C to +105°C. |
