Texas Instruments

The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV031A accepts low voltage LVTTL or LVCMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE®function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. The DS90LV031A is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV031A accepts low voltage LVTTL or LVCMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition the driver supports a TRI-STATE®function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The EN and EN* inputs allow active Low or active High control of the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV031A and companion line receiver (DS90LV032A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications.

The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100 Ω) input Fail-safe. The receiver output is HIGH for all fail-safe conditions. The DS90LV032A and companion LVDS line driver (for example, DS90LV031A) provide a new alternative to high power PECL or ECL devices for high speed point-to-point interface applications. The DS90LV032A is a quad CMOS differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV032A accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100 Ω) input Fail-safe. The receiver output is HIGH for all fail-safe conditions. The DS90LV032A and companion LVDS line driver (for example, DS90LV031A) provide a new alternative to high power PECL or ECL devices for high speed point-to-point interface applications.

The DS90LV047A device is a quad CMOS flow-through differential line driver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV047A accepts low voltage TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition, the driver supports a TRI-STATE function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The DS90LV047A has a flow-through pinout for easy PCB layout. The EN and EN∗inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV047A and companion line receiver (DS90LV048A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications. The DS90LV047A device is a quad CMOS flow-through differential line driver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV047A accepts low voltage TTL/CMOS input levels and translates them to low voltage (350 mV) differential output signals. In addition, the driver supports a TRI-STATE function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state of 13 mW typical. The DS90LV047A has a flow-through pinout for easy PCB layout. The EN and EN∗inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four drivers. The DS90LV047A and companion line receiver (DS90LV048A) provide a new alternative to high power psuedo-ECL devices for high speed point-to-point interface applications.

The DS90LV048A device is a quad CMOS flow-through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV048A accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100-Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DS90LV048A has a flow-through pinout for easy PCB layout. The EN and EN∗inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four receivers. The DS90LV048A and companion LVDS line driver (for example, DS90LV047A) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications. The DS90LV048A device is a quad CMOS flow-through differential line receiver designed for applications requiring ultra-low power dissipation and high data rates. The device is designed to support data rates in excess of 400 Mbps (200 MHz) using Low Voltage Differential Signaling (LVDS) technology. The DS90LV048A accepts low voltage (350 mV typical) differential input signals and translates them to 3-V CMOS output levels. The receiver supports a TRI-STATE function that may be used to multiplex outputs. The receiver also supports open, shorted, and terminated (100-Ω) input fail-safe. The receiver output is HIGH for all fail-safe conditions. The DS90LV048A has a flow-through pinout for easy PCB layout. The EN and EN∗inputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four receivers. The DS90LV048A and companion LVDS line driver (for example, DS90LV047A) provide a new alternative to high-power PECL/ECL devices for high-speed point-to-point interface applications.

The DS90LV049H is a dual CMOS differential line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and high data throughput. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV049H TSSOP package allows for flow-through routing for easy PCB layout. The DS90LV049H drivers accept LVTTL/LVCMOS signals and translate them to LVDS signals. The receivers accept LVDS signals and translate them to 3-V CMOS signals. The LVDS input buffers have internal fail-safe biasing that places the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049H supports a TRI-STATE function for a low idle power state when the device is not in use. The EN andENinputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four gates. The DS90LV049H is a dual CMOS differential line driver-receiver pair designed for applications requiring ultra low power dissipation, exceptional noise immunity, and high data throughput. The device is designed to support data rates in excess of 400 Mbps utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LV049H TSSOP package allows for flow-through routing for easy PCB layout. The DS90LV049H drivers accept LVTTL/LVCMOS signals and translate them to LVDS signals. The receivers accept LVDS signals and translate them to 3-V CMOS signals. The LVDS input buffers have internal fail-safe biasing that places the outputs to a known H (high) state for floating receiver inputs. In addition, the DS90LV049H supports a TRI-STATE function for a low idle power state when the device is not in use. The EN andENinputs are ANDed together and control the TRI-STATE outputs. The enables are common to all four gates.

DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz. The DS90LV110A accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATE by use of the enable pin. For more details, please refer to the APPLICATION INFORMATION section of this datasheet. DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz. The DS90LV110A accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATE by use of the enable pin. For more details, please refer to the APPLICATION INFORMATION section of this datasheet.

The DS90LV804 is a four channel 800 Mbps LVDS buffer/repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme. In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables. The DS90LV804, available in the WQFN (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance. An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE, low power mode. The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations. The DS90LV804 is a four channel 800 Mbps LVDS buffer/repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme. In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables. The DS90LV804, available in the WQFN (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance. An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE, low power mode. The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations.

The DS90LVRA2 is a dual CMOS differential line receiver designed for applications requiring high input common mode range, high data rates and CMOS output with slew rate control. The device is designed to support data rates of 600 Mbps (300 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LVRA2 accepts low voltage (350 mV typical) differential input signals and translates them to 1.8 V CMOS output levels depending on power supply voltage. The DS90LVRA2 has a flow-through design for easy PCB layout. The DS90LVRA2 and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications. The DS90LVRA2 is a dual CMOS differential line receiver designed for applications requiring high input common mode range, high data rates and CMOS output with slew rate control. The device is designed to support data rates of 600 Mbps (300 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. The DS90LVRA2 accepts low voltage (350 mV typical) differential input signals and translates them to 1.8 V CMOS output levels depending on power supply voltage. The DS90LVRA2 has a flow-through design for easy PCB layout. The DS90LVRA2 and companion LVDS line driver DS90LV027AQ provide a new alternative to high power PECL/ECL devices for high speed point-to-point interface applications.

The DS90UA101-Q1 Serializer, in conjunction with the DS90UA102-Q1 Deserializer, provides a solution for distribution of digital audio in multi-channel audio systems. It transmits a high-speed serialized interface with an embedded clock over a single shielded twisted pair or coaxial cable. The serial bus scheme supports high speed forward data transmission and low speed bidirectional control channel over the link. Consolidation of digital audio, general-purpose IO, and control signals over a single differential pair reduces the interconnect size and weight, while also reducing design challenges related to skew and system latency. The DS90UA101-Q1 Serializer embeds the clock and level shifts the signals to high-speed low-voltage differential signaling. The device serializes up to eight digital audio data inputs, word/frame sync, bit clock, and system clock. Four dedicated general purpose input pins and four general purpose output pins allow flexible implementation of control and interrupt signals to and from remote devices. The DS90UA101-Q1 Serializer, in conjunction with the DS90UA102-Q1 Deserializer, provides a solution for distribution of digital audio in multi-channel audio systems. It transmits a high-speed serialized interface with an embedded clock over a single shielded twisted pair or coaxial cable. The serial bus scheme supports high speed forward data transmission and low speed bidirectional control channel over the link. Consolidation of digital audio, general-purpose IO, and control signals over a single differential pair reduces the interconnect size and weight, while also reducing design challenges related to skew and system latency. The DS90UA101-Q1 Serializer embeds the clock and level shifts the signals to high-speed low-voltage differential signaling. The device serializes up to eight digital audio data inputs, word/frame sync, bit clock, and system clock. Four dedicated general purpose input pins and four general purpose output pins allow flexible implementation of control and interrupt signals to and from remote devices.

The DS90UA102-Q1 Deserializer, in conjunction with the DS90UA101-Q1 Serializer, provides a solution for distribution of digital audio in multi-channel audio systems. It receives a high-speed serialized interface with an embedded clock over a single shielded twisted pair or coaxial cable. The serial bus scheme supports high speed forward data transmission and low speed bidirectional control channel over the link. Consolidation of digital audio, general-purpose IO, and control signals over a single differential pair reduces the interconnect size and weight, while also reducing design challenges related to skew and system latency. The DS90UA102-Q1 Deserializer extracts the clock and level shifts the signals from high-speed low voltage differential signaling to single-ended LVCMOS. The device outputs up to eight digital audio data channels, word/frame sync, bit clock, and system clock. Four dedicated general purpose input pins and four general purpose output pins allow flexible implementation of control and interrupt signals to and from remote devices. Adaptive equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces medium-induced deterministic jitter. The DS90UA102-Q1 Deserializer, in conjunction with the DS90UA101-Q1 Serializer, provides a solution for distribution of digital audio in multi-channel audio systems. It receives a high-speed serialized interface with an embedded clock over a single shielded twisted pair or coaxial cable. The serial bus scheme supports high speed forward data transmission and low speed bidirectional control channel over the link. Consolidation of digital audio, general-purpose IO, and control signals over a single differential pair reduces the interconnect size and weight, while also reducing design challenges related to skew and system latency. The DS90UA102-Q1 Deserializer extracts the clock and level shifts the signals from high-speed low voltage differential signaling to single-ended LVCMOS. The device outputs up to eight digital audio data channels, word/frame sync, bit clock, and system clock. Four dedicated general purpose input pins and four general purpose output pins allow flexible implementation of control and interrupt signals to and from remote devices. Adaptive equalization of the serial input stream provides compensation for transmission medium losses of the cable and reduces medium-induced deterministic jitter.