DS90UB924-Q1 Series

5 MHz to 96 MHz 24-bit Color FPD-Link III to OpenLDI Deserializer

Catalog

5 MHz to 96 MHz 24-bit Color FPD-Link III to OpenLDI Deserializer

Part	Qualification	Function	Supplier Device Package	Number of Outputs	Grade	Output Type	Mounting Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Inputs	Package / Case	Input Type	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments DS90UB924TRHSTQ1	AEC-Q100	Deserializer	48-WQFN (7x7)	4	Automotive	LVDS	Surface Mount	3.6 V	3 V	4	48-WFQFN Exposed Pad	LVCMOS	105 °C	-40 °C
Texas Instruments DS90UB924TRHSRQ1	AEC-Q100	Deserializer	48-WQFN (7x7)	4	Automotive	LVDS	Surface Mount	3.6 V	3 V	4	48-WFQFN Exposed Pad	LVCMOS	105 °C	-40 °C

Catalog

5 MHz to 96 MHz 24-bit Color FPD-Link III to OpenLDI Deserializer

Key Features

• Qualified for Automotive Applications AEC-Q100Device Temperature Grade 2: –40°C to+105°C Ambient Operating TemperatureRangeDevice HBM ESD Classification Level ±8 kVDevice CDM ESD Classification Level C65-MHz to 96-MHz Pixel Clock SupportBidirectional Control Channel Interface with I2C-Compatible Serial Control BusLow EMI OpenLDI Video OutputSupports High Definition (720p) Digital VideoRGB888 + VS, HS, DE and I2S Audio SupportedUp to 4 I2S Digital Audio Outputs for SurroundSound Applications4 Bidirectional GPIO Channels With 2 Dedicated PinsSingle 3.3-V Supply With 1.8-V or 3.3-VCompatible LVCMOS I/O InterfaceDC-Balanced and Scrambled Data withEmbedded ClockAdaptive Cable EqualizationInternal Pattern GenerationBackward Compatible ModesQualified for Automotive Applications AEC-Q100Device Temperature Grade 2: –40°C to+105°C Ambient Operating TemperatureRangeDevice HBM ESD Classification Level ±8 kVDevice CDM ESD Classification Level C65-MHz to 96-MHz Pixel Clock SupportBidirectional Control Channel Interface with I2C-Compatible Serial Control BusLow EMI OpenLDI Video OutputSupports High Definition (720p) Digital VideoRGB888 + VS, HS, DE and I2S Audio SupportedUp to 4 I2S Digital Audio Outputs for SurroundSound Applications4 Bidirectional GPIO Channels With 2 Dedicated PinsSingle 3.3-V Supply With 1.8-V or 3.3-VCompatible LVCMOS I/O InterfaceDC-Balanced and Scrambled Data withEmbedded ClockAdaptive Cable EqualizationInternal Pattern GenerationBackward Compatible Modes

Description

The DS90UB924-Q1 deserializer, in conjunction with a DS90UB921-Q1, DS90UB925Q-Q1, DS90UB927Q-Q1, DS90UB929-Q1, DS90UB949-Q1, or DS90UB947-Q1 serializer, provides a solution for distribution of digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI), and I2S audio data. The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design. Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling. The DS90UB924-Q1 deserializer, in conjunction with a DS90UB921-Q1, DS90UB925Q-Q1, DS90UB927Q-Q1, DS90UB929-Q1, DS90UB949-Q1, or DS90UB947-Q1 serializer, provides a solution for distribution of digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI), and I2S audio data. The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design. Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling.