Texas Instruments

The DS90UB633A-Q1 device offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single coaxial cable or differential pair. The DS90UB633A-Q1 device incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer/deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical-bidirectional control channel information. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects. The DS90UB633A-Q1 device offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single coaxial cable or differential pair. The DS90UB633A-Q1 device incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer/deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This device is ideally suited for driving video data requiring up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical-bidirectional control channel information. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.

The DS90UB635-Q1 serializer is part of TI’s FPD-Link III device family designed to support high-speed raw data sensors including 2.3MP imagers at 60-fps and as well as 4MP, 30-fps cameras, satellite RADAR, LIDAR, and Time-of-Flight (ToF) sensors. The chip delivers a 4.16-Gbps forward channel and an ultra-low latency, 50-Mbps bidirectional control channel and supports power over a single coax (PoC) or STP cable. The DS90UB635-Q1 features advanced data protection and diagnostic features to support ADAS and autonomous driving. Together with a companion deserializer, the DS90UB635-Q1 delivers precise multi-camera sensor clock and sensor synchronization. The DS90UB635-Q1 is fully AEC-Q100 qualified with a -40°C to 105°C wide temperature range. The serializer comes in a small 5-mm × 5-mm VQFN package for space-constrained sensor applications. The DS90UB635-Q1 serializer is part of TI’s FPD-Link III device family designed to support high-speed raw data sensors including 2.3MP imagers at 60-fps and as well as 4MP, 30-fps cameras, satellite RADAR, LIDAR, and Time-of-Flight (ToF) sensors. The chip delivers a 4.16-Gbps forward channel and an ultra-low latency, 50-Mbps bidirectional control channel and supports power over a single coax (PoC) or STP cable. The DS90UB635-Q1 features advanced data protection and diagnostic features to support ADAS and autonomous driving. Together with a companion deserializer, the DS90UB635-Q1 delivers precise multi-camera sensor clock and sensor synchronization. The DS90UB635-Q1 is fully AEC-Q100 qualified with a -40°C to 105°C wide temperature range. The serializer comes in a small 5-mm × 5-mm VQFN package for space-constrained sensor applications.

The DS90UB638-Q1 is a versatile deserializer capable of receiving serialized sensor data from a source through an FPD-Link III interface. When paired with a DS90UB635-Q1 serializer, the DS90UB638-Q1 receives data from imagers, supporting 2MP/60fps and 4MP/30fps cameras, as well as satellite RADAR and other sensors such as ToF and LIDAR. Data is received and presented at a MIPI CSI-2 compliant output for interconnect to a downstream processor. When configuring the CSI-2 interface for 2-lane operation, a duplicate MIPI CSI-2 clock lane is available to provide a replicated output. Replication mode creates two copies of the received video stream for data logging and parallel processing. The DS90UB638-Q1 is AEC-Q100 qualified and designed to receive data across a 50-Ω, single-ended coaxial. The deserializer is ideal for Power-over-Coax applications and the receive equalizer automatically adapts to compensate for cable loss characteristics with no additional programming required, including degradation over time. Each FPD-Link III interface includes a separate low latency bidirectional control channel (BCC) that continuously conveys I2C, GPIO, and other control information. GPIO signals purposed for sensor synchronization and diagnostic features also make use of the BCC. The DS90UB638-Q1 is a versatile deserializer capable of receiving serialized sensor data from a source through an FPD-Link III interface. When paired with a DS90UB635-Q1 serializer, the DS90UB638-Q1 receives data from imagers, supporting 2MP/60fps and 4MP/30fps cameras, as well as satellite RADAR and other sensors such as ToF and LIDAR. Data is received and presented at a MIPI CSI-2 compliant output for interconnect to a downstream processor. When configuring the CSI-2 interface for 2-lane operation, a duplicate MIPI CSI-2 clock lane is available to provide a replicated output. Replication mode creates two copies of the received video stream for data logging and parallel processing. The DS90UB638-Q1 is AEC-Q100 qualified and designed to receive data across a 50-Ω, single-ended coaxial. The deserializer is ideal for Power-over-Coax applications and the receive equalizer automatically adapts to compensate for cable loss characteristics with no additional programming required, including degradation over time. Each FPD-Link III interface includes a separate low latency bidirectional control channel (BCC) that continuously conveys I2C, GPIO, and other control information. GPIO signals purposed for sensor synchronization and diagnostic features also make use of the BCC.

The DS90UB662-Q1 is a versatile sensor hub capable of connecting serialized sensor data received from four independent video data streams through a FPD-Link III interface. When paired with a DS90UB633A-Q1 or DS90UB63x CSI-2 serializer, the DS90UB662-Q1 receives data from 1-Megapixel image sensors supporting 720p/800p/960p/1MP resolution at 30-Hz or 60-Hz frame rates. Data is received and aggregated into a MIPI CSI-2 compliant output for interconnect to a downstream processor. The DS90UB662-Q1 includes four FPD-Link III deserializers, each enabling a connection through cost-effective 50-Ω single-ended coaxial or 100-Ω differential STP cables. The receive equalizers automatically adapt to compensate for cable loss characteristics, including degradation over time. Each of the FPD-Link III interfaces also includes a separate low latency bidirectional control channel that continuously conveys I2C, GPIOs, and other control information. General-purpose I/O signals such as those required for camera synchronization and diagnostics features also make use of this bidirectional control channel. The DS90UB662-Q1 is AEC-Q100 qualified for automotive applications and is offered in a cost-effective and space-saving 64-pin VQFN package. The DS90UB662-Q1 is a versatile sensor hub capable of connecting serialized sensor data received from four independent video data streams through a FPD-Link III interface. When paired with a DS90UB633A-Q1 or DS90UB63x CSI-2 serializer, the DS90UB662-Q1 receives data from 1-Megapixel image sensors supporting 720p/800p/960p/1MP resolution at 30-Hz or 60-Hz frame rates. Data is received and aggregated into a MIPI CSI-2 compliant output for interconnect to a downstream processor. The DS90UB662-Q1 includes four FPD-Link III deserializers, each enabling a connection through cost-effective 50-Ω single-ended coaxial or 100-Ω differential STP cables. The receive equalizers automatically adapt to compensate for cable loss characteristics, including degradation over time. Each of the FPD-Link III interfaces also includes a separate low latency bidirectional control channel that continuously conveys I2C, GPIOs, and other control information. General-purpose I/O signals such as those required for camera synchronization and diagnostics features also make use of this bidirectional control channel. The DS90UB662-Q1 is AEC-Q100 qualified for automotive applications and is offered in a cost-effective and space-saving 64-pin VQFN package.

The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bidirectional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. A Serializer standby function provides a low power-savings mode with a remote wake up capability for signaling of a remote device. The Serializer is offered in a 32-pin WQFN (5mm x 5mm) package, and Deserializer is offered in a 40-pin WQFN (6mm x 6mm) package. The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bidirectional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. A Serializer standby function provides a low power-savings mode with a remote wake up capability for signaling of a remote device. The Serializer is offered in a 32-pin WQFN (5mm x 5mm) package, and Deserializer is offered in a 40-pin WQFN (6mm x 6mm) package.

The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bidirectional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. A Serializer standby function provides a low power-savings mode with a remote wake up capability for signaling of a remote device. The Serializer is offered in a 32-pin WQFN (5mm x 5mm) package, and Deserializer is offered in a 40-pin WQFN (6mm x 6mm) package. The DS90UB901Q/DS90UB902Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The Serializer/Deserializer pair is targeted for direct connections between automotive camera systems and Host Controller/Electronic Control Unit (ECU). The primary transport sends 16 bits of image data over a single high-speed serial stream together with a low latency bidirectional control channel transport that supports I2C. Included with the 16-bit payload is a selectable data integrity option for CRC (Cyclic Redundancy Check) to monitor transmission link errors. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control information without the dependency of video blanking intervals. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. A Serializer standby function provides a low power-savings mode with a remote wake up capability for signaling of a remote device. The Serializer is offered in a 32-pin WQFN (5mm x 5mm) package, and Deserializer is offered in a 40-pin WQFN (6mm x 6mm) package.

The DS90UB903Q/DS90UB904Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB903Q/904Q incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with bidirectional control channel bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages. The DS90UB903Q/DS90UB904Q chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB903Q/904Q incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The Serializer/ Deserializer pair is targeted for direct connections between graphics host controller and displays modules. This chipset is ideally suited for driving video data to displays requiring 18-bit color depth (RGB666 + HS, VS, and DE) along with bidirectional control channel bus. The primary transport converts 21 bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port. Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, the Deserializer inputs provide equalization control to compensate for loss from the media over longer distances. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. The Serializer is offered in a 40-pin lead in WQFN and Deserializer is offered in a 48-pin WQFN packages.

The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period. Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is offered in a 48-pin WQFN package. The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period. Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is offered in a 48-pin WQFN package.

The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period. Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is offered in a 48-pin WQFN package. The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus. There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period. Using TI’s embedded-clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing paths, which reduces PCB layers, cable width, connector size and pins. In addition, the deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. The Serializer is offered in a 32-pin WQFN package and the deserializer is offered in a 48-pin WQFN package.

The DS90UB921-Q1 serializer, in conjunction with a DS90UB922-Q1, DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB948-Q1, or DS90UB940-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications. The chipset is ideally suited for automotive video-display systems with WVGA and HD formats. The DS90UB921-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This chipset translates a parallel interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed video data transmission and bidirectional control communication over a single link. Consolidation of video data and control over a single differential pair (or single wire) reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design. The DS90UB921-Q1 serializer embeds the clock, DC scrambles & balances the data payload, and level shifts the signals to high-speed low voltage differential (or single-ended) signaling. Up to 24 data bits are serialized along the video control signals. EMI is minimized by the use of low voltage swing signaling, data scrambling and randomization and spread spectrum clocking compatibility. Remote interrupts from the downstream deserializer are mirrored to a local output pin. The DS90UB921-Q1 serializer, in conjunction with a DS90UB922-Q1, DS90UB926Q-Q1, DS90UB928Q-Q1, DS90UB948-Q1, or DS90UB940-Q1 deserializer, provides a complete digital interface for concurrent transmission of high-speed video, audio, and control data for automotive display and image sensing applications. The chipset is ideally suited for automotive video-display systems with WVGA and HD formats. The DS90UB921-Q1 incorporates an embedded bidirectional control channel and low latency GPIO controls. This chipset translates a parallel interface into a single pair high-speed serialized interface. The serial bus scheme, FPD-Link III, supports full duplex of high-speed video data transmission and bidirectional control communication over a single link. Consolidation of video data and control over a single differential pair (or single wire) reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design. The DS90UB921-Q1 serializer embeds the clock, DC scrambles & balances the data payload, and level shifts the signals to high-speed low voltage differential (or single-ended) signaling. Up to 24 data bits are serialized along the video control signals. EMI is minimized by the use of low voltage swing signaling, data scrambling and randomization and spread spectrum clocking compatibility. Remote interrupts from the downstream deserializer are mirrored to a local output pin.